Transcript slides

BIST / Test-Decompressor Design
using Combinational Test Spectrum
Nitin Yogi
Vishwani D. Agrawal
Auburn University, Dept. of Elec. & Comp. Eng.
Auburn, AL 36849, U.S.A.
13th IEEE / VSI VLSI Design and Test Symposium
Bangalore, India
July 10, 2009
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Outline
Problem Definition
 Proposed Design Method




Results



Spectral Analysis
BIST Architecture
Results without reseeding
Results with reseeding
Conclusion
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Problem Definition

To design a Test Pattern Generator (TPG) for
Built-In Self Test (BIST) of combinational
circuits achieving the following goals:

Given a set of pre-generated test vectors,
replicate their effects in hardware

Low area overhead

Low test application times
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Proposed Design Methodology
Pre-generated
test vectors
Step 1
Spectral properties
Step 2
Preprocess test
vectors
Determine
prominent spectral
components by
spectral analysis
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BIST
implementation
BIST TPG
gate-level
netlist
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Walsh Functions and Hadamard Matrix
w0
Walsh functions (order 3)
w1
w2
• Walsh functions: a complete
orthogonal set of basis functions
that can represent any arbitrary bitstream.
• Walsh functions form the rows of a
Hadamard matrix.
w3
w4
H(3) =
w5
w6
w7
time
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Example of Hadamard
matrix of order 3
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Test Vectors and Bit-streams
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Input 3
Input 4
Input 5
1
0
0
1
0
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0
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1
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0
1
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1
1
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1
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1
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0
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1
Input J
Input 2
Vector K →
1
0
1
1
0
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1
Outputs
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1
0
1
0
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Time
Vector 1 →
Vector 2 →
Vector 3 →
Vector 4 →
Vector 5 →
Input 1
Circuit Under Test (CUT)
A binary
bit-stream
to be
spectrally
analyzed
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Spectrum: Input 1 of circuit s5378
250
Magnitude
200
150
100
50
Theoretical
random noise
level (16)
0
1
21
41
61
81
101
121
141
161
181
201
221
241
Spectral Coefficients
Spectrum of ATPG bit-stream applied to input 1 of circuit s5378
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Spectrum: Input 9 of circuit s5378
250
Magnitude
200
150
100
50
Theoretical
random noise
level (16)
0
1
21
41
61
81
101
121
141
161
181
201
221
241
Spectral Coefficients
Spectrum of ATPG bit-stream applied to input 9 of circuit s5378
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Effect of Noise
Effect of noise (500 samples)
Gate-level faults
detected by 226
ATPG vectors
0.04
0.035
Frequency
0.03
0.025
ST = 0
0.02
0.015
ST = 1
0.01
ST = 5
0.005
0
3100
3150
3200
3250
3300
3350
Number of gate-level stuck-at faults detected
3400
ST = 9
More faults
detected
 Noise inserted in ATPG vectors, generated for a sample of faults
(RTLthan
original
vectors
faults), for s5378 circuit, using increasing spectral threshold (ST)
values

(i.e., increasing noise)
226 ATPG vectors for1602 RTL faults
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BIST Architecture
SC
System
clock
N-bit counter
with XOR
gates
Hadamard
wave
generator
System clock
3
BIST clock
1
1
Spectral
component
synthesizer
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Input 1
Input 2
Randomizer
1
Weighted
pseudo-random
bit-streams
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Proportion:
SC1 = 0.5
SC2 = 0.5
1
Bit-stream
To
Proportion:
of spectral
Noise
SC1 = 0.25
CUT
SC2
component Cellular Automata SC
inserted
2 = 0.25
BIST SC
SC
bit-stream
3 = 0.5
Register with
3
Weighted
random
clock
AND-OR gates
bit-stream (W = 0.25)
Weighted pseudorandom pattern
generator
2
Hadamard
Components
Weighted
random
bit-stream
(W=0.5)
Weighted
random
bit-stream
(W=0.5)
To
CUT
Input 3
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Hadamard Wave Generator
LSB
CLK
3-bit
down
counter;
N flip-flops
For H(N)
Logic ‘1’
W0
FF1
W1
FF2
W2
W3
W4
FF3
MSB
W5
W6
W7
C. K. Yuen, “New Walsh-Function Generator,” Electronics Letters, vol. 7, p. 605, 1971.
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Generation of Weighted Random Bit-streams
P1=0.5
P1=0.25
P1=0.625
P1=0.5
Cellular
Automata
Register
M Flip-flops
P1=0.5
P1=0.5
P1=0.75
P1=0.5
P1=0.875
P1=0.9375
P1=0.5
P1=0.5
Circuit
No. of PI
No. of Flip-flops
Hadamard wave gen. (N)
CA register (M)
c7552
207
6
24
s15850 (comb.)
600
7
28
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Spectral BIST Results and Area Overhead
Test coverage results without reseeding (64000 vectors)
Circuit
Random
vectors
Weighted
Random
vectors
Spectral
BIST
ATPG
Coverage
(No. of vecs)
c7552
97.41%
97.86%
99.81%
100% (247)
s15850
(combinational)
96.81%
97.41%
98.77%
100% (530)
Area overhead comparison
Spectral BIST
PRPG
Circuit
No. of
gates in
circuit
No. of
gates
% Area
overhead
No. of
gates
% Area
overhead
c7552
3513
976
27.78
830
23.63
s15850
(combinational)
9772
2672
27.34
2400
24.56
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Test Coverage vs Number of Vectors
c7552
100
Spectral
BIST
Test coverage
99
98
97
Weighted
Random
96
95
94
Random
93
0
10000
20000
30000
40000
50000
60000
Test vectors
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Test Coverage vs Number of Vectors
s15850
100
Spectral
BIST
98
Test coverage
96
94
Weighted
Random
92
90
Random
88
86
0
10000
20000
30000
40000
50000
60000
Test vectors
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Reseeding of Spectral TPG
Flip-flops
Data from
external
tester
Parallel interface
Spectral BIST /
Decompressor
BIST /
Decompressor
Logic
To
CUT
Serial
scan
interface
Mode of operation
Function
External Tester Mode (ETM)
One-seed-per-test vector operation
Hybrid BIST Mode (HBM)
Used to generate test vectors and reseed flip-flops periodically
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Spectral TPG Results with Reseeding
Comparison of test data volume and test time for c7552
No. of
inputs
Test
data
volume
(bits)
No. of
tester
cycles
No. of
system
clock
cycles
Test
time
(us)†
247
207
51129
247
0
2
247
1
51129
51129
0
511
ETM (parallel)
197
30
5910
197
0
2
ETM (serial)
197
1
5910
5910
0
59
HBM (parallel)
33
30
990
33
8034
8
HBM (serial)
33
1
990
990
8034
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Mode of test application
No. of
vecs./
seeds
Conventional (parallel)
Conventional (serial)
Spectral
BIST
† assuming tester clock period Ttester=10ns and on-chip system clock period Tclk=1ns
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Spectral TPG Results with Reseeding
Comparison of test data volume and test time for s15850 (combinational)
No. of
inputs
Test
data
volume
(bits)
No. of
tester
cycles
No. of
system
clock
cycles
Test
time
(us)†
530
600
318000
530
0
5
530
1
318000
318000
0
3180
ETM (parallel)
455
35
15925
455
0
5
ETM (serial)
455
1
15925
15925
0
159
HBM (parallel)
134
35
4690
134
20129
21
HBM (serial)
134
1
4690
4690
20129
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Mode of test application
No. of
vecs./
seeds
Conventional (parallel)
Conventional (serial)
Spectral
BIST
† assuming tester clock period Ttester=10ns and on-chip system clock period Tclk=1ns
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Conclusion

Proposed a TPG design methodology for combinational
circuits using spectral techniques.


Designed TPG exhibits the following:




Also proposed a reshuffling algorithm to enhance spectral
components.
Higher test coverage than random and weighted random vectors
for equal number of test vectors.
Encouraging test data compression capabilities up to 95%.
An order of magnitude reduction in test application time.
Issues to address:

Slightly high area overhead

Overhead might reduce by:
 Implementation on larger circuits
 Optimum selection of spectral components by reshuffling algorithm

Increase in test time for parallel HBM

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Optimum seeds and intervals for reseeding can reduce the test time.
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Thank you.
Questions please?
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Pre-processing of Test Vectors
Reshuffling Algorithm:
Input Data and Parameters:
NI: No of inputs
NV: No. of vectors
V(1:NV,1:NI): Test vector Set of dimensions NV x NI
hd: Dimension of Hadamard matrix
H: Hadamard transform matrix of dimension 2hd x 2hd
Procedure:
Vector set V appended with redundant vectors to make weighting of
bit-streams of all inputs = 0.5
for i=1 to NI
Perform spectral analysis on bit-stream of input i: S = V(:,i) x H;
Pick the prominent spectral component Sp(i) from S
Rearrange vector set V such that maximum bits in the
bit- streams of inputs 1 to i match with the picked prominent
spectral components Sp(1 to i) respectively.
end
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