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Encoder 8 to 3--Truth Table
•An input is Active High
D7 D6 D5 D4 D3 D2 D1 D0
Q2 Q1 Q0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
1
1
|
1
|
0
0
|
0
0
|
0
0
|
0
1
Encoder 8 to 3--Equations
•In the previous truth table each line selected
0 through 7 generates it’s own binary code
such as a 1 is a 001, 5 is a 101 and so on.
•Boolean Equations for Outputs
Q2 = D4 + D5 + D6 +D7
Q1 = D2 + D3 + D6 + D7
Q0 = D1 + D3 + D5 + D7
Priority Encoder II
•Priority Encoder Equations
Q2 = D7 + D6 + D5 + D4
Q1 = D7 + D6 + !D5!D4D3 + !D5!D4D2
Q0 = D7 + !D6D5 + !D6!D4D3 + !D6!D4!D2D1
十進位數對BCD編碼器
表6-6
十進位值
0
1
2
3
4
5
6
7
8
9
BCD 碼
A3
0
0
0
0
0
0
0
0
1
1
A2
A1
0
0
0
0
1
1
1
1
0
0
A0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
P332
Summary
Encoders
pp313An encoder accepts an active logic level on one of
its inputs and converts it to a coded output, such as BCD or
binary.
The decimal to BCD is an encoder
with an input for each of the ten
decimal digits and four outputs that
represent the BCD code for the active
digit. The basic logic diagram is
shown. There is no zero input
because the outputs are all LOW
when the input is zero.
Floyd, Digital Fundamentals, 10th ed
1
A0
2
3
4
5
6
7
8
A1
A2
A3
9
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Encoders
Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.
The top two OR gates have ones as indicated with
the red lines. Thus the output is 0111.
1 0
1
2 0
1
3
1
4
5
6
7
8
9
Floyd, Digital Fundamentals, 10th ed
0
0
0
0
0
0
0
0
A0
A1
A2
A3
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
priority
Encoders
pp314 The 74HC147 is an example of an IC encoder. It is
has ten active-LOW inputs and converts the active input to
V
an active-LOW BCD output.
CC
(16)
This device is offers additional
flexibility in that it is a priority
encoder. This means that if more
than one input is active, the one
with the highest order decimal
digit will be active.
Decimal
input
(11)
(12)
(13)
(1)
(2)
(3)
(4)
(5)
(10)
HPRI/BCD
1
2
3
4
5
6
7
8
9
74HC147
The next slide shows an application …
Floyd, Digital Fundamentals, 10th ed
1
2
4
8
(9)
(7)
(6)
(14)
BCD
output
(8)
GND
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
應用實例
P334
Summary
VCC
Encoders
pp316
Keyboard
encoder
R7
7
R8
8
9
HPRI/BCD
R4
4
R5
5
R1
1
0
R6
6
R2
2
R0
Floyd, Digital Fundamentals, 10th ed
R9
R3
1
2
3
4
5
6
7
8
9
1
2
4
8
BCD complement of
key press
74HC147
3
The zero line is not needed by the
encoder, but may be used by other
circuits to detect a key press.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
二進位數對格雷碼和格雷碼對二進位數的轉換
6-12
(a)利用XOR閘將二進位數0101轉換成格雷碼。
(b)利用XOR閘將格雷碼1011轉換成二進位數。
解：
(a)01012的格雷碼為
0111。見圖6-31(a)。
(b)格雷碼1011的二進位
數為11012。見圖
6-31(b)。
圖6-31
相關問題 要將8位元二進位數轉換成格雷碼，須要用到幾個
XOR閘？
P337
Summary
Code converters
pp318There are various code converters that change one
code to another. Two examples are the four bit binary-toGray converter and the Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
0
1
0
1
0
1
1
0
0
Binary-to-Gray
Floyd, Digital Fundamentals, 10th ed
1
LSB
LSB
MSB
0
1
1
1
0
0
MSB
Gray-to-Binary
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
6-7 多工器(資料選擇器)
P339
Multiplexer Logic
• A MUX is called a N to 1 MUX that requires M Select inputs such that
the number of data inputs N = 2M.
• For example a 4 to 1 MUX requires 2 Select inputs (S1 and S0).


 


Y  D0 S1 S0  D1 S1S0  D2 S1 S0  D3 S1S0 
Summary
Multiplexers
pp320 A multiplexer (MUX) selects one data line from
two or more input lines and routes data from the selected
line to the output. The particular data line that is selected
is determined by the select inputs.
Two select lines are shown
here to choose any of the
four data inputs.
S0
Data
select S1
Which data line is selected if
S1S0 = 10? D2
Floyd, Digital Fundamentals, 10th ed
D0
D1
Data
D
inputs D2
3
0
1
MUX
0
1
0
1
2
3
Data
output
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
6-8 解多工器
解多工器 (DEMUX) 的功能基本上是和多工器相反的
。它由一傳輸線取得資料，再將資料分配到數條輸出線。
解多工器又稱作資料分配器。
研讀本節之後，您將具備下列能力：
 說明解多工器的基本運作。
 做出一解多工器之資料輸入波形及資料選擇輸入線波形
的時序圖。
P346
DemuX 1-4
Channel Select
Signal
s1
s0
Y0
Y1
Y2
Y3
D
 
Y 1  D S S 
Y 2   D S S 
Y 0   D S1 S 0
1
1
0
0
Y 3  D S1S 0 
6-8 解多工器
例6-16
(續)
解：
注意，資料選擇線會依照二進位數的順序將輸入資
料傳送到 D0 , D1 , D2 ， D3 和輸出端，如圖6-39中的輸
出波形所示。
相關問題 若將 S0 和 S1 波形的波形反相，試畫出此解
多工器的時序圖。
P347
6-8 解多工器
圖6-39所示為串列資料輸入波形 ( 輸入資料 ) 和資
6-16
料選擇輸入線
( 和 ) 波形。試畫出圖6-38解多工器
到
D0
S1
S0
的資料輸出波形。
D3
圖6-39
P346
Summary
Demultiplexers
pp329 A demultiplexer (DEMUX) performs the opposite
function from a MUX. It switches data from one input line
to two or more data lines depending on the select inputs.
The 74LS138 was introduced
previously as a decoder but can also
serve as a DEMUX. When
connected as a DEMUX, data is
applied to one of the enable inputs,
and routed to the selected output
line depending on the select
variables. Note that the outputs are
active-LOW as illustrated in the
following example…
Floyd, Digital Fundamentals, 10th ed
DEMUX
Data
select
lines
Enable
inputs
A0
A1
A2
G1
G2A
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Data
outputs
74LS138
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Demultiplexers
Determine the outputs, given the
inputs shown.
The output logic is opposite to the input
because of the active-LOW convention. (Red
shows the selected line).
DEMUX
A0
A1
A2
Data
select
lines
Enable
inputs
G1
G2A
G2B
74LS138
Floyd, Digital Fundamentals, 10th ed
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Data
outputs
A0
A1
A2
G1
G2A LOW
G2B LOW
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
基本同位產生/檢查邏輯電路
產生
檢查
P348
4 Bit Parity Generator& Checker
Summary
Parity Generators/Checkers
pp330 Parity is an error detection method
that uses an extra bit appended to a group
of bits to force them to be either odd or
even. In even parity, the total number of
ones is even; in odd parity the total
number of ones is odd.
The ASCII letter S is 1010011. Show the parity
bit for the letter S with odd and even parity.
S with odd parity = 11010011
S with even parity = 01010011
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
具有錯誤偵測功能的資料傳送系統
P351
1. For the full-adder shown, assume the input bits are as
shown with A = 0, B = 0, Cin = 1. The Sum and Cout will be
a. Sum = 0 Cout = 0
b. Sum = 0 Cout = 1
0
A
c. Sum = 1 Cout = 0
0
B
d. Sum = 1 Cout = 1
S
S
A
Cout
B
S
S
Sum
Cout
1
Cout
© 2008 Pearson Education
2. The output will be LOW if
a. A < B
b. A > B
A1
B1
A2
B2
c. both a and b are
correct
A3
B3
d. A = B
A4
B4
Output
© 2008 Pearson Education
4. Assume you want to decode the binary number 0011 with
an active-LOW decoder. The missing gate should be
a. an AND gate
b. an OR gate
A0
A1
A2
?
X
c. a NAND gate
d. a NOR gate
A3
© 2008 Pearson Education
5. Assume you want to decode the binary number 0011 with
an active-HIGH decoder. The missing gate should be
a. an AND gate
b. an OR gate
A0
A1
A2
?
X
c. a NAND gate
d. a NOR gate
A3
© 2008 Pearson Education
7. The decimal-to-binary encoder shown does not have a
zero input. This is because
a. when zero is the input,
all lines should be LOW
1
2
3
b. zero is not important
c. zero will produce
illegal logic levels
d. another encoder is used
for zero
A0
4
5
6
7
8
A1
A2
A3
9
© 2008 Pearson Education
8. If the data select lines of the MUX are S1S0 = 11, the
output will be
a. LOW
b. HIGH
c. equal to D0
d. equal to D3
MUX
S0
Data
select S1
0
1
D0
D1
Data
D
inputs D2
3
0
1
2
3
Data
output
© 2008 Pearson Education
9. The 74138 decoder can also be used as
a. an encoder
b. a DEMUX
c. a MUX
d. none of the above
© 2008 Pearson Education