Transcript Fast waveform digitization with the DRS chip Stefan Ritt Paul Scherrer Institute, Switzerland

Fast waveform digitization
with the DRS chip
Stefan Ritt
Paul Scherrer Institute, Switzerland
The MEG Experiment at PSI
Needed:
Goal:
m → e
at 10-13
• Pile-up rejection (BG from 108 µ
decays in unsegmented calorimeter)
• ADC dynamic range of 12 bit
• TDC resolution of 40 ps
• Analog pipeline (L1 trigger) ~300ns
• 3000 channels
PMT
sum
0.511 MeV
51.5 MeV
t
~100ns
2 GS
12 Bit
100 $/Chn
Liq. Xe Scintillation
Detector
Liq. Xe Scintillation
Detector
Thin Superconducting Coil

Stopping Target
Muon Beam
e+

Timing Counter
e+
Drift Chamber
Drift Chamber
1m
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Domino Sampling Chip Principle
0.2-2 ns
Inverter “Domino” ring chain
IN
Waveform
stored
Clock
Shift Register
Out
FADC
33 MHz
“Time stretcher” GHz  MHz
Keep Domino wave running in a circular fashion and
stop by trigger  Domino Ring Sampler (DRS)
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The DRS3 Chip
domino wave
8 inputs
Design Properties:
Reference
clock
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•
•
•
•
•
•
shift register
MUX
12 channels at 1024 bins
Cascadable 6x2k, …, 1x12k bins
Sampling speed 10 MHz – 5 GHz
Readout speed 33 MHz
ROI readout (3 ms for 100 bins)
Fabricated in 0.25 mm 1P5M MMC
process (UMC), 5 x 5 mm2
• Radiation Hard (CMS Pixel library,
R. Horisberger)
• Power consumption: 50 mW @ 2 GHz
• Packaged chip costs:
35 $ / chn. (MPW run)
3 $ / chn. (SPW run)
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PLL Stabilization
• Temperature coefficient: 500ps / ºC
• Jitter after PLL stabilization: ~200ps / turn
• Improved timing with clock reference
channel: <100ps
Domino Wave Pulse
Reference Clock
~200 psec
PLL
Vspeed
R. Paoletti, N. Turini, R. Pegna
MAGIC collaboration
External
Common
Reference
Clock (1-4 MHz)
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Linearity and Noise
• “Fixed pattern noise”: 6 mV (RMS)
• Noise after offset correction
(in FPGA code during readout):
0.25 mV (RMS)  12 bit SNR
DRS3 Nonlinearity
2
Deviation [mV]
• Careful design gave linearity 0.1V … 1.1V
better ±0.5 mV, Tc ≈ 50 ppm
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
Uin [V]
• Bandwidth: 450 MHz, to be
improved with small design
change for mass production
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VPC & USB boards
32 channels input
DRS3
USB interface
board
DRS2
14-bit flash ADC
AD9248
PSI general purpose
VME board with 2 PPC cores
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Comparison with other chips
V1729 (CAEN)
MATACQ chip
LABRADOR
Univ. Hawaii
DRS3
Bandwidth (-3db)
300 MHz
> 1000 MHz
450 MHz
Sampling frequency
1 or 2 GHz
10 MHz … 3.5 GHz
10 MHz … 5 GHz
Full scale range
±0.5 V
+0.4 …2.1 V
+0.1 … 1.1V
Effective #bits
12 bit
10 bit
12 bit
Sample points
1 x 2520
9 x 256
12 x 1024
Channel per board
4
N/A
32
Digitization
5 MHz
N/A
33 MHz
Readout dead time
650 ms
150 ms
3 ms – 370 ms
Integral nonlinearity ± 0.1 %
± 0.1 %
± 0.05%
Radiation hard
No
Yes (chip)
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No
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hits
MEG with DRS2
“Virtual
oscilloscope”
Moving average baseline
• Drift chamber
anode &
cathode signals
@ 500 MHz
• Moving baseline
• 50 ns pile-up
rejection
• Cluster density
 particle ID
Crosstalk removal by subtracting empty channel
Template fit
Final noise level: 0.32 mV (bin), 0.07 mV (baseline)
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Real-time aspects
How to get rid again of the waveform data?
Managing the waveform data
• 3000 Channels @ 100 Hz @ 1024 bins @ 24 bit = 880 MB/sec
• All data needs calibration
• Need extensive data compression
• Event rate can be improved if compression moves “upstream”
Optimize implementation
MIDAS DAQ
DRS
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FPGA
PPC
PPC
Fiber
84 MB/s
VME
Front-end PC
Gbit
Ethernet
Back-end PC
CPU
100 MB/s
CPU
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CPU
CPU
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Compression algorithms in FPGA
• Zero suppression:
hit if max. value > average + 3 x s
• Readout window: start / width in
respect to trigger
• Pile-up flag: Zero-crossings of first
derivation
• Re-binning 4:1, 8:1, 16:1
• ADC: Numerical integral of hit
over baseline
• TDC: Only simple threshold (usable to
recognize accidentals) and time-overthreshold
• Spline calibration
• Waveform fitting
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Not feasible
in FPGA
Must be
implemented
in PC
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0.5 ns bins
4 ns bins
TOT
12
DAQ cluster
clock
start
stop
sync
pE5 area
‘cave’
Ancillary
system
Trigger
Front-End PCs
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
Trigger
Trigger
Trigger
20
MHz
clock
Ready
3 crates
DRS
DRS
DRS
DRS
DRS
DRS
Gigabit
Ethernet
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
Trigger
Hit
registers
storage
6 crates
9 VME creates
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Event
builder
On-line farm
11 dual-Xenon PCs with hyper-threading
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Event rate before MT
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Multi-threading model
Zero-copy
ring buffers
VME
Round-Robin
distribution
Calibration
Thread
Calibration
Thread
VME
Transfer
Thread
Collector
Thread
Calibration
Thread
Calibration
Thread
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Network
Ring buffer functions
in MIDAS:
rb_create()
rb_get_wp()
rb_increment_wp()
rb_get_rp()
rb_increment_rp()
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Event rate with 4 threads
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Conclusions
• Waveform digitizing with DRS chip opens new exiting possibilities
for pile-up recognition and pulse-shape discrimination
• This technology can completely eliminate the needs for traditional
ADCs and TDCs at attractive costs
• Switching from ADC/TDC data to waveforms increases the demand
for computing power and storage dramatically and requires new
strategies for data reduction
• Effective multithreading will be the future in RT computing
VME board with DRS chip will probably
be available from CAEN by end 2007
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