Transcript CREAM: the new NA62 calorimeter readout board Stefano Venditti on behalf of the NA62 LKr group PH-ESE seminar - 03/12/2013

CREAM: the new NA62 calorimeter readout board
Stefano Venditti
on behalf of the NA62 LKr group
PH-ESE seminar - 03/12/2013
OUTLOOK
• The K→πνν decay
• The NA62 experiment
• The NA62 liquid Krypton calorimeter
• CREAM: The NA62 Calorimeter REAdout Module
• Board layout
• Firmware properties
• Analog signal characterization @ CERN
• Outcome of in situ tests
• Conclusions
Stefano Venditti - CERN PH-ESE
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THE K→πνν DECAY CHANNEL
No FCNC → contribution to K→πνν decay from penguin diagrams only
• Top quark contribution dominance
• CKM matrix suppression ( Vts*Vtd)
→ high sensitivity to new physics
• Hadronic matrix element can be
related to K→eπ0ν decay BR
• CKM triangle measurement
SM PREDICTIONS:
[Brod et al.
- Phys. Rev D 83, (2011) 034030]
BR(K     )  (7.81 0.75 0.29) 1011
BR(KL   0 )  (2.43 0.39  0.06) 1011
PRESENT EXPERIMENTAL STATUS:
15
BR(K     )  (1.7311..05
) 1010
• 7 candidate events from 2 experiments
(E787, E949 @ Brookhaven)
• Probability of all events being background ~ 10-3
BR( K L   0 )  2.6 108
(E391a @ KEK)
HADRON MATRIX ELEMENT Stefano Venditti - CERN PH-ESE
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THE NA62 EXPERIMENT
NA62 is the last from a long tradition of fixed-target Kaon
experiments in the North Area (NA) @ CERN
 Fixed target experiment: 1.1x1012 Hz 400 GeV SPS protons on a Be target
 Outgoing charged particles (750 MHz, ~6% K+) selected in momentum
(75±1% GeV/c) and direction (X,Y spread<100 μrad) through achromats
 10 MHz decay rate on detectors (mainly from K+)
GOAL: collect O(100) K+→π+νν events with S/B~10
REQUIREMENTS: 1013 K decays collected, >1012 BG reduction, 10% precision on BG
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K+→π+νν SELECTION SCHEME
•
•
•
•
•
•
•
•
•
Signal in KTAG compatible with a Kaon
One reconstructed track in the Gigatracker, no activity in the CHANTI
One reconstructed track in the Straws matched in time with a Kaon in GTK
Signal in RICH compatible with a charged pion
No signals in the LAVs, IRC, SAC compatible with a γ
1 deposit compatible with a pion in the LKr, no additional γs
No signal compatible with in MUV3, pion shower in MUV1+2, signal in CHOD
Pion vertex within the first 60 meters of the decay volume
15 GeV/c < Pπ < 35 GeV/c
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K+→π+νν SELECTION SCHEME
•
•
•
•
•
•
•
•
•
Signal in KTAG compatible with a Kaon
One reconstructed track in the Gigatracker, no activity in the CHANTI
One reconstructed track in the Straws matched in time with a Kaon in GTK
Signal in RICH compatible with a charged pion
No signals in the LAVs, IRC, SAC compatible with a γ
1 deposit compatible with a pion in the LKr, no additional γs
No signal compatible with in MUV3, pion shower in MUV1+2, signal in CHOD
Pion vertex within the first 60 meters of the decay volume
15 GeV/c < Pπ < 35 GeV/c
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K+→π+νν selection scheme
•
•
•
•
•
•
•
•
•
Signal in KTAG compatible with a Kaon
One reconstructed track in the Gigatracker, no activity in the CHANTI
One reconstructed track in the Straws matched in time with a Kaon in GTK
Signal in RICH compatible with a charged pion
No signals in the LAVs, IRC, SAC compatible with a γ
1 deposit compatible with a pion in the LKr, no additional γs
No signal compatible with in MUV3, pion shower in MUV1+2, signal in CHOD
Pion vertex within the first 60 meters of the decay volume
15 GeV/c < Pπ < 35 GeV/c
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K+→π+νν SELECTION SCHEME
•
•
•
•
•
•
•
•
•
Signal in KTAG compatible with a Kaon
One reconstructed track in the Gigatracker, no activity in the CHANTI
One reconstructed track in the Straws matched in time with a Kaon in GTK
Signal in RICH compatible with a charged pion
No signals in the LAVs, IRC, SAC compatible with a γ
1 deposit compatible with a pion in the LKr, no additional γs
No signal compatible with in MUV3, pion shower in MUV1+2, signal in CHOD
Pion vertex within the first 60 meters of the decay volume
15 GeV/c < Pπ < 35 GeV/c
Stefano Venditti - CERN PH-ESE
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K+→π+νν SELECTION SCHEME
•
•
•
•
•
•
•
•
•
Signal in KTAG compatible with a Kaon
One reconstructed track in the Gigatracker, no activity in the CHANTI
One reconstructed track in the Straws matched in time with a Kaon in GTK
Signal in RICH compatible with a charged pion
No signals in the LAVs, IRC, SAC compatible with a γ
1 deposit compatible with a pion in the LKr, no additional γs
No signal compatible with in MUV3, pion shower in MUV1+2, signal in CHOD
Pion vertex within the first 60 meters of the decay volume
15 GeV/c < Pπ < 35 GeV/c
Stefano Venditti - CERN PH-ESE
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K+→π+νν SELECTION SCHEME
•
•
•
•
•
•
•
•
•
Signal in KTAG compatible with a Kaon
One reconstructed track in the Gigatracker, no activity in the CHANTI
One reconstructed track in the Straws matched in time with a Kaon in GTK
Signal in RICH compatible with a charged pion
No signals in the LAVs, IRC, SAC compatible with a γ
1 deposit compatible with a pion in the LKr, no additional γs
No signal compatible with in MUV3, pion shower in MUV1+2, signal in CHOD
Pion vertex within the first 60 meters of the decay volume
15 GeV/c < Pπ < 35 GeV/c
Stefano Venditti - CERN PH-ESE
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K+→π+νν SELECTION SCHEME
•
•
•
•
•
•
•
•
•
Signal in KTAG compatible with a Kaon
One reconstructed track in the Gigatracker, no activity in the CHANTI
One reconstructed track in the Straws matched in time with a Kaon in GTK
Signal in RICH compatible with a charged pion
No signals in the LAVs, IRC, SAC compatible with a γ
1 deposit compatible with a pion in the LKr, no additional γs
No signal compatible with in MUV3, pion shower in MUV1+2, signal in CHOD
Pion vertex within the first 60 meters of the decay volume
15 GeV/c < Pπ < 35 GeV/c
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K+→π+νν SELECTION SCHEME
•
•
•
•
•
•
•
•
•
Signal in KTAG compatible with a Kaon
One reconstructed track in the Gigatracker, no activity in the CHANTI
One reconstructed track in the Straws matched in time with a Kaon in GTK
Signal in RICH compatible with a charged pion
No signals in the LAVs, IRC, SAC compatible with a γ
1 deposit compatible with a pion in the LKr, no additional γs
No signal compatible with in MUV3, pion shower in MUV1+2, signal in CHOD
Pion vertex within the first 60 meters of the decay volume
15 GeV/c < Pπ < 35 GeV/c
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THE NA62 TDAQ SYSTEM
Na62 will apply 3 trigger levels to events before writing data on disk
• L0T: FPGA based, fixed
latency ~ 1 ms
10 MHz:
Physics
events
• L1T: PC based, all data
available except LKr’s, max
latency: ~1 s
1 MHz
• L2T: final decision taken
using data from all detectors,
max latency ~ burst length
100 KHz
10 KHz:
On-disk
events
The TALK BOARD processes TRIGGER PRIMITIVES
from fast detectors and takes the final L0T decision.
The TALK cannot be used at regime because of some
intrinsic limitations. 2 SOLUTIONS are currently under test
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TEL62 & TDCB
TEL62
• Major upgrade of TELL1 board (LHCB)
• 4 PP-FPGAs, 1 SL-FPGA (Stratix III)
• 4 200 pin connectors for mezzanines
• 4 DDR2 (2 Gbytes each)
• Quad-GBE output mezzanine
Data is collected from TDCBs and stored
in the DDR waiting for the L0 trigger; the
proper data is then sent to the PC farm
through the GBE. The SAME DATA is
used to produce L0T primitives
TDC BOARD (TDCB)
• Developed by NA62 Pisa group
• 4 CERN HPTDCs onboard
• 1 Altera Cyclone III
• 2x 1MB SRAM
TDC data is buffered,timestamped
and sent to TEL62. TDC emulation
in the FPGA available
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THE NA62 LKr CALORIMETER
The NA62 experiment will reuse the NA48 liquid Krypton
calorimeter (LKr hereafter) in order to:
• Veto particles in the forward direction
• Provide a high-precision measurement of the
electromagnetic energy deposits
DETECTOR INFORMATION
• 10 m3 liquid Krypton calorimeter, 1.25 m deep (27 X0)
• 13284 2x2 cm2 cells, projecting geometry
• Signal is formed by the collection of electrons ionized by
the passage of a particle in the Krypton (~ 2.5 μA/GeV)
• Preamplifiers inside the LKr tank
• Calibration system mounted on the LKr tank
THE LKR UNDER CONSTRUCTION
CELL’S ZIG-ZAG SHAPE
LKR SECTION (1/4)
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THE CREAM BOARD
The Calorimeter REAdout Module (CREAM) is a 6U VME board developped by CAEN
upon CERN specifications.It will replace the old LKr readout used in the NA48 experiment
FRONT PANEL
Ethernet port:
L1 data output
Trigger sum links:
Data to LKr L0T
processor
8 Gbytes DDR3 module
FPGA:
Altera
Stratix IV
P0 custom
bus
2 x 16 channels
input connectors
14 bit ADCs
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THE CREAM BOARD
THE MOTHERBOARD
digital logic, trigger, data buffer (8GB DDR3)
THE DAUGHTERBOARD
analog signal shaping, digitisation
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THE CREAM BOARD FUNCTIONS
• INPUT SIGNAL SHAPING: the 2.7
μs long triangular signal from LKr
channels is shaped into a 70 ns
FWHM pseudo-Gaussian signal
• DIGITISATION: shaped signals are
digitised @ 40 MHz by octal 14 bit
ADCs and copied in a circular buffer
• FIRST TRIGGER LEVEL (L0T):
upon reception of the L0T signal
through the custom P0 VME
backplane, data is moved from the
circular buffer to the L0 buffer
• SECOND TRIGGER LEVEL (L1T):
when a L1T signal is received through
a Multiple request UDP packet (MRP)
data is sent to the PC farm
• TRIGGER SUM LINKS: the sums of
the digitised samples from two groups
of 16 channels each are serialized
inside the FPGA and sent to the LKr
L0 processor
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THE CREAM BOARD FUNCTIONS
• INPUT SIGNAL SHAPING: the 2.7
μs long triangular signal from LKr
channels is shaped into a 70 ns
FWHM pseudo-Gaussian signal
• DIGITISATION: shaped signals are
digitised @ 40 MHz by octal 14 bit
ADCs and copied in a circular buffer
• FIRST TRIGGER LEVEL (L0T):
upon reception of the L0T signal
through the custom P0 VME
backplane, data is moved from the
circular buffer to the L0 buffer
• SECOND TRIGGER LEVEL (L1T):
when a L1T signal is received through
a Multiple request UDP packet (MRP)
data is sent to the PC farm
• TRIGGER SUM LINKS: the sums of
the digitised samples from two groups
of 16 channels each are serialized
inside the FPGA and sent to the LKr
L0 processor
Stefano Venditti - CERN PH-ESE
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THE CREAM BOARD FUNCTIONS
• INPUT SIGNAL SHAPING: the 2.7
μs long triangular signal from LKr
channels is shaped into a 70 ns
FWHM pseudo-Gaussian signal
• DIGITISATION: shaped signals are
digitised @ 40 MHz by octal 14 bit
ADCs and copied in a circular buffer
• FIRST TRIGGER LEVEL (L0T):
upon reception of the L0T signal
through the custom P0 VME
backplane, data is moved from the
circular buffer to the L0 buffer
• SECOND TRIGGER LEVEL (L1T):
when a L1T signal is received through
a Multiple request UDP packet (MRP)
data is sent to the PC farm
• TRIGGER SUM LINKS: the sums of
the digitised samples from two groups
of 16 channels each are serialized
inside the FPGA and sent to the LKr
L0 processor
Stefano Venditti - CERN PH-ESE
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THE CREAM BOARD FUNCTIONS
• INPUT SIGNAL SHAPING: the 2.7
μs long triangular signal from LKr
channels is shaped into a 70 ns
FWHM pseudo-Gaussian signal
• DIGITISATION: shaped signals are
digitised @ 40 MHz by octal 14 bit
ADCs and copied in a circular buffer
• FIRST TRIGGER LEVEL (L0T):
upon reception of the L0T signal
through the custom P0 VME
backplane, data is moved from the
circular buffer to the L0 buffer
• SECOND TRIGGER LEVEL (L1T):
when a L1T signal is received through
a Multiple request UDP packet (MRP)
data is sent to the PC farm
• TRIGGER SUM LINKS: the sums of
the digitised samples from two groups
of 16 channels each are serialized
inside the FPGA and sent to the LKr
L0 processor
Stefano Venditti - CERN PH-ESE
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THE CREAM BOARD FUNCTIONS
• INPUT SIGNAL SHAPING: the 2.7
μs long triangular signal from LKr
channels is shaped into a 70 ns
FWHM pseudo-Gaussian signal
• DIGITISATION: shaped signals are
digitised @ 40 MHz by octal 14 bit
ADCs and copied in a circular buffer
• FIRST TRIGGER LEVEL (L0T):
upon reception of the L0T signal
through the custom P0 VME
backplane, data is moved from the
circular buffer to the L0 buffer
• SECOND TRIGGER LEVEL (L1T):
when a L1T signal is received through
a Multiple request UDP packet (MRP)
data is sent to the PC farm
• TRIGGER SUM LINKS: the sums of
the digitised samples from two groups
of 16 channels each are serialized
inside the FPGA and sent to the LKr
L0 processor
Stefano Venditti - CERN PH-ESE
11
THE CREAM BOARD FUNCTIONS
• INPUT SIGNAL SHAPING: the 2.7
μs long triangular signal from LKr
channels is shaped into a 70 ns
FWHM pseudo-Gaussian signal
• DIGITISATION: shaped signals are
digitised @ 40 MHz by octal 14 bit
ADCs and copied in a circular buffer
• FIRST TRIGGER LEVEL (L0T):
upon reception of the L0T signal
through the custom P0 VME
backplane, data is moved from the
circular buffer to the L0 buffer
• SECOND TRIGGER LEVEL (L1T):
when a L1T signal is received through
a Multiple request UDP packet (MRP)
data is sent to the PC farm
• TRIGGER SUM LINKS: the sums of
the digitised samples from two groups
of 16 channels each are serialized
inside the FPGA and sent to the LKr
L0 processor
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CREAM CRATE ORGANIZATION
• 16 CREAMs will be housed in a VME crate
• 28 CREAM crates, organised in 8 racks, will readout the whole calorimeter
• The TTC-LKr board is placed in the 11th slot of each crate
SLOW CONTROL: up to
8 bridges (CAEN
VX2718) daisy chained,
four links controlled by
a single A3818 PCIe
card
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THE TTC-LKr BOARD
• 6U VME64x board, Xilinx Spartan-6 FPGA onboard
• TTC-FMC mezzanine (CERN) using the ADN2814 clock-data recovery IC
FUNCTIONS
• Distribution of 40 MHz clock,
L0T signal, start/end of burst
and broadcast commands to
the CREAMs in a crate
• Crate ID number
• Reception of CHOKE and
ERROR signals from CREAMs
and their transmission to the
L0T processor
TTC SOURCES
• optical 160 Mbps BPM
encoded bit-stream
• electrical front-panel inputs
• internal rate-programmable
TTC signal generator
• generated by a VME access
The selected source is available for the CREAMs on the P0 backplane.
All TTC signals are synchronised with the selected clock reference
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INPUT SIGNAL
The signals from the LKr channels go into the
CREAM through two connectors delivering 16
differential pairs each to the CREAM input
16 CHANNELS
CONNECTORS
PLUGGED IN A
CREAM
The signal is shaped into a 70 ns FWHM Gaussian by shapers (20 ns differentiation
+Bessel filter) mounted on the CREAM daughterboard
THE SHAPING CIRCUIT AND THE ADC CHIP
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DIGITISATION
The shaped signals are digitised by four commercial octal 14-bit ADCs (AD9257 from
Analog Devices) mounted on the daughterboard. Radiation hardness not required
MAIN CHIP FEATURES
• 14 bits dynamic range
• 2V p-p input voltage range
• SNR 75.5 dB
• DNL ± 0.6, INL ± 1.1 (typical)
• 55 mW per channel
• Activable internal patterns
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FPGA & DDR3
FPGA
The firmware is housed in an ALTERA
Stratix IV FPGA mod. EP4SGX180
• Equivalent LEs: 175750
• Registers: 140600
• Embedded memory: 11430 Kb
TOTAL RESOURCE USAGE: ~32%
(max 40% requested in specifications)
8 GB DDR3 SODIMM MODULE
• Both circular and the L0 buffer are implemented
in the DDR3 module directly connected to the
FPGA
• Circular buffer is 1M x 256-bit wide, allowing for
12.5 ms (>> L0T latency) data storage
• L0 buffer is 255M x 256 bit wide, allowing for 16
s (> spill length) data storage at the nominal
100 KHz L1T rate and 8 samples/trigger
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THE TSL
The CREAM system data output is too large to be fully exploited for the L0T decision
Each CREAM computes Trigger Sums (TS) and sends them to the LKr L0T processor
• Samples from 2 groups of 4x4 channels summed every 25 ns
• Baseline subtracted and gain correction applied to each channel of the sum
• The two sums (16 bits each, the 2 LSBs are dropped) serialised on two pairs of a
standard RJ45 connector
• Serialization inside FPGA following Texas Instruments DS92LV18 IC coding
• The TELDES board, plugged on a TEL62 and hosting 16 DS92LV18, deserializes the
sums and sends the data to the TEL62 PPs.
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CREAM L0 TRIGGER PROCESSING
Sampled data are housed in a 12.5ms wide circular buffer built inside the DDR3.
Data is continuously copied in the buffer, waiting for a L0 trigger
32x2 byte
32x2 byte
32x2 byte
32x2 byte
samples
samples
samples
samples
EXAMPLE
• samples collected: 4
• latency: 10 clock cycles
32x2 byte
32x2 byte
samples
samples
CIRCULAR BUFFER
………..
SAMPLES MOVED TO L0 BUFFER
L0T LATENCY (FIXED)
L0T reception time
When a CREAM receives a L0 trigger, a configurable number of samples is extracted
from the circular buffer at fixed latency and moved to the L0 buffer
EVENT NUMBERS
0
1
2
3
4
5
6
7
8
9
10
11
12
data
data
data
data
data
data
data
data
data
data
data
data
data
L0 BUFFER
Events are univocally identified by their event number and timestamp,both reset at SOB
s
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CREAM L1 TRIGGER PROCESSING
Once the PC farm has taken a L1 decision, a L1 request is issued to all CREAMs
through Multi-Request Packets (MRP). Each CREAM sends the data corresponding
to the specific event number requested, through Sub-Detector Event (SDE) packets
EVENT NUMBERS
0
1
2
3
4
5
6
7
8
9
10
11
12
data
data
data
data
data
data
data
data
data
data
data
data
data
L0 BUFFER
MRPs from PC farm are
received and decoded
in the FPGA
Data is extracted from
L0 buffer,given a header
and sent to the PC farm
as UDP packet
Data is available for L1
requests during the
whole burst duration
FPGA
SDE
MRP
Ev.
number12
0
<ETHERNET
Ev.
number
8
4
Ev. number 8
0
Ev.
Ev.number
number12
4
Stefano Venditti - CERN PH-ESE
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CREAM L1 TRIGGER PROCESSING
• The 16 CREAMs in a crate are connected to a 10 Gbit switch, that allows to
receive/send packets from/to the PC farm
• The CREAMs cain join multicast groups: the PC farm sends to this group only one
data request, which is forwarded to all CREAMs belonging to the group at switch level.
10 Gbit switch
(one per crate)
Stefano Venditti - CERN PH-ESE
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L1 PACKETS FORMAT
PACKET FORMATS
REQUEST TO CREAM: MRP (Multi-Request Packet) UDP packet
Number of events
Total MRP length
header
sender’s IP address
Reserved
Timestamp
Fine time
Reserved
(LSB: ZS on)
L1T word
Reserved
L1 request
L0T word
Event number
…………..
DATA FROM CREAM: SDE (Sub-Detector Event) UDP packet
Source ID
Event number
Reserved
Event Length
header
Timestamp
Reserved
L0T word
Crate and slot ID
Data
31
0
Stefano Venditti - CERN PH-ESE
SDE header is standard
for different Source IDs
(NA62 detectors), data
content is custom
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L1 PACKETS FORMAT
DATA PACKET (ZS and NZS mode)
MSB1: L0 readout
MSB2: ZS readout
#SAMPLES
Data Length
data header
Active channels (0xffffffff in NZS mode)
Sample 0 (1° active ch.)
Sample 1 (1° active ch.)
….
….
Sample N-1(1° active ch.)
Sample N (1° active ch.)
Sample 0 (2° active ch.)
Sample 1 (2° active ch.)
….
Sample N-1(last active ch.)
LKr data
….
Sample N (last active ch.)
Checksum
31
0
• Empty packet sent if no channel complies with the zero-suppression threshold
• Possibility to readout events at L0 (no need for MRPs, lower request rate)
• Up to 256 samples/L1 request can be sent
• Use of jumbo frames implemented
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L1 PACKETS FORMAT
L1 MECHANISM AT WORK (WIRESHARK OUTPUT)
MRP size = 10
MRP
SDEs
MRP
SDEs
MRP
SDEs
MRP
MRP from PC IP to Multicast IP Address (all CREAMs)
SDE from CREAM IP to PC IP (taken from MRP)
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ZERO SUPPRESSION
The CREAM bandwidth can be reduced by performing zero-suppressed(ZS) L1 requests.
In this mode the triggered samples of a channel are sent if at least one of its samples is
above a programmable threshold. Several zero-suppression scenarios will be tested:
ZS scheme
DRAWBACK
ZS requests only
Thorough calibration needed
L0-based mode
Highly dependent on the L0 algorithm
Double request mode
Total achievable L1 rate reduced
Double request mode: a first ZS request is issued to all CREAMs in multicast mode; a
second NZS request is issued only to modules wich are part of specific regions of interest
CREAMs sending
non-empty zerosuppressed data
upon first request
CREAMs receiving
second request and
sending non zerosuppressed data
1° REQUEST (ZS)
2° REQUEST (NZS)
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SPECIAL TRIGGERS
The TTC broadcast signal is used to deliver L0 triggers to the acquisition system
CODE
TRIGGER TYPE
CREAM ACTION
0b0xxxxx
Physics
Readout data
0b100001
Synchronization
Send special frame
0b100010
Start of burst (SOB)
Send special frame
0b100011
End of burst (SOB)
Send EOB report
0b100100
Choke on
Send special frame
0b100101
Choke off
Send special frame
0b100110
Error on
Send special frame
0b100111
Error off
Send special frame
0b101000
Monitoring
Send monitoring data
0b10110x
Random
Readout data
0b11xxxx
Calibration
Readout data
CHOKE/ERROR MECHANISM:
A CREAM is in a
critical or in error
condition (e.g. a
L0 fifo almost full)
CHOKE line
raised on P0
LKR-TTC
CHOKE
received by
CREAMs,
packet sent
L0T Processor:
Send CHOKE and
stop L0s
Stefano Venditti - CERN PH-ESE
LKR-TTC
If critical state
solved, lower
CHOKE (L0s
restarted), if
not keep it up
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TESTS @ CERN
First 4 CREAMs @ CERN in March 2013
FIRST GOAL: verify that the specifications on
the quality of the analog signal are met
MOST IMPORTANT FEATURES TESTED:
• ENOB (>10 required)
• Cross-talk (<-70 dB required)
• Non-linearities (Differential < 2 LSBs,
Integral < 5 LSBs required)
• Non-coherent noise (< 2 LSBs) and coherent
noise(< 10% non-coherent noise)
• Signal shape (after shaping) is 70 ns±10%
FWHM pseudo-Gaussian with ±1 ns
uniformity
Continuous acquisition mode used in the tests
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TESTS @ CERN: ENOB
• 5 MHz input sine wave synchronous with the 40 MHz
clock to CREAMs
• 5 MHz narrow-band pass filters before CREAM input
• FFT and data analysis with ROOT
• ENOB of all channels well within specification
5 MHz
ZOOM
5 MHz
SINE
CLOCK TO
CREAM
FFT ON CREAM DATA (65K SAMPLES)
10 MHz
ZOOM
15 MHz
ZOOM
Stefano Venditti - CERN PH-ESE
NARROW-BAND
PASS FILTERS
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TESTS @ CERN: ENOB
ENOB DISTRIBUTION FOR 1 CHANNEL
(1K EVENTS)
ENOB - 32 CHANNELS OF A CREAM
Stefano Venditti - CERN PH-ESE
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TESTS @ CERN: CROSS-TALK
• 5 MHz input sine wave, FFT of non-pulsed
channels computed
• Low-band pass filters used
• Only cross-talk of neighbor channels is slightly
above specifications (<-70 dB)
• The cross-talk is on the connector, not on the PCB
LOW-PASS
FILTERS
CROSS TALK SHAPE: points are averages of samples
CROSS-TALK
(NEIGHBOR
CHANNEL)
Stefano Venditti - CERN PH-ESE
PULSED CHANNEL
(~FULL SCALE)
5 COUNTS
0.5 COUNTS
CROSS TALK
(NEXT-TO
NEIGHBOR
CHANNEL)
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TESTS @ CERN: CROSS-TALK
FFT SPECTRA
PULSED CHANNEL
NEIGHBOR CHANNELS
NEXT-TO NEIGHBOR
CHANNELS
Stefano Venditti - CERN PH-ESE
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TESTS AT CERN: NON-LINEARITIES
• Non linearities measured using a sine wave histogram test
(Ting, Liu, IEEE Tr. On Instr. & Meas., Vol. 57, N. 2)
• Uncoherent sampling, sine amplitude > dynamic range to populate all ADC values
• Given the number of events and the population of the first and last bins, the theoretical
distribution in case of perfect linearity is computed and compared with data
i
• INL and DNL well within the specifications
H (i)
DNL(i) 
a
exp
H theo (i)
 1 INL(i)   DNL(i)
k 1
b
c
a,b) INL and DNL values (1 channel), full ADC range
c) Theoretical (RED) and experimental (BLUE)
distributions of sample values
INL and DNL max values – 32 CREAM channels
Stefano Venditti - CERN PH-ESE
31
TESTS @ CERN: NOISE
• The pedestal value of each channel is measured, pedestal mean values are removed
• Two groups of 16 channels (even and odd) are formed
• The ditribution of the sum (difference) of the two groups → total noise σSUM (total non-
coherent noise σDIFF) → coherent(σCOH) and non-coherent(σNCOH) noise/channel
• σNCOH and σCOH within the specifications (σNCOH < 2 LSB,
 COH 
σCOH < 10% σNCOH)
2
2
 SUM
  DIFF
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 NCOH 
 DIFF
32
PEDESTALS – 16 CHANNELS
CHANNEL SUM AND DIFFERENCE DISTRIBUTION
Stefano Venditti - CERN PH-ESE
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SIGNAL SHAPE AND UNIFORMITY
• LKr-like signal replicated using Tektronix AFG9252 pulse generators
• Trigger mode used: 8 samples extracted using sync signal from the generator,
delayed by the CREAM latency
• Both the signal width and its uniformity are within specifications
WIDTH DISTRIBUTION (1 CHANNEL)
TRIGGERED SAMPLES
0 1 2 3 4 5 6 7
8 SAMPLES
Stefano Venditti - CERN PH-ESE
33
TECHNICAL AND “DRY” RUNS
December 2012: a daughterboard tested on an Altera test-bench (no motherboard
available at the time), 8 channels readout. Real LKr signals from particles collected.
TESTED FEATURES
• Shaping: LKr-signals turned
into Gaussian 70 ns wide ones
•Sampling: digised samples
collected on disk and analysed
7 3
CELLS POSITION
ON LKR SURFACE
6 2
5 1
4 0
ADC
COUNTS
SAMPLE INDEX
Stefano Venditti - CERN PH-ESE
34
TECHNICAL AND “DRY” RUNS
Summer 2013: two CREAMs were used in the NA62 “dry” run (i.e. a run without
particles, mainly meant to test the readout system)
TESTED FEATURES
• Network: MRP reception by
CREAMs, CREAM data
received by the PC farm and
written on disk
• TTC-LKr: tested for the first
time
• Switch: tested for the first
time (not at the full required
bandwidth)
Stefano Venditti - CERN PH-ESE
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TECHNICAL AND “DRY” RUNS
November/December 2013: 16 CREAMs (a whole crate) were tested at the NA62 site.
TESTED FEATURES
• Trigger sum links: the TELDES
board correctly received and
deserialized data from CREAMs
• Network: multicast requests sent
to all CREAMs, switch tested at the
required bandwidth
• L1 rate: 100 KHz rate L1 triggers
sent to CREAMs, no packet loss
detected
TESTS STILL ONGOING!
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CONCLUSIONS
• Exhaustive tests of the prototypes and preproduction modules have shown full
compliance with specifications
•“Green light” for the production will be probably given this week
NEXT STEPS
•1st production batch (220 modules) delivery is foreseen in February 2014;
• 2nd production batch (220 modules) delivery is foreseen in May 2014;
• Production tests foreseen in March-June 2014;
• LKr readout commissioning is foreseen during summer 2014;
In addition, we are very pleased to mention that our measurements show that overall
performance of such complex module developed by CAEN is beyond our specifications
and expectations, and now we are very confident that, in spite of some delay, the project
is in very good shape. In particular we would like to thank:
Luca Colombini
Annalisa Mati
Stefano Petrucci
Andrea Romboli
Carlo Tintori
Stefano Venditti - CERN PH-ESE
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