Transcript 0.37 mS/mm In0.53Ga0.47As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain Uttam Singisetti*, Mark A.

0.37 mS/mm In0.53Ga0.47As MOSFET with 5 nm channel and
self-aligned epitaxial raised source/drain
Uttam Singisetti*, Mark A. Wistey, Greg J. Burek, Ashish K. Baraskar, Joel Cagnon, B. J.
Thibeault, S. Stemmer, A.C. Gossard, and M.J.W. Rodwell
ECE and Materials Departments
University of California, Santa Barbara, CA
Eun Ji Kim, Byungha Shin, and Paul C McIntyre
Materials Science and Engineering, Stanford University, Stanford, CA
Yong-ju Lee
Intel Corporation, Santa Clara, CA
2009 Device Research Conference
Pennsylvania State University, State College, PA
*[email protected]
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Outline
• Motivation: III-V MOSFETs
• Approach: Self-aligned source/drain by MBE regrowth
• FET and contacts Results
• Conclusion and future work
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Why III-V MOSFETs
Silicon MOSFETs:
Gate oxide may limit <16 nm scaling
Id / Wg ~ cox(Vg-Vth)vinj
Id / Qtransit ~ vinj / Lg
IBM 45nm NMOS
Narayan et al, VLSI 2006
Alternative: In0.53Ga0.47As channel MOSFETs
low m* (0.041 mo) → high injection velocity (~ 2×107 cm/s)*
→ increase
drive current, decreased CV/I
*
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Enoki et al , EDL 1990
DRC 2009
Target device structure
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Al O
Energy (eV)
2
2
3
1
0
-1
InGaAs
InAlAs
-2
-3
-4
0
Target 22 nm gate length
50
100
150
Y (Ang.)
200
250
Control of short-channel effects  vertical scaling
1 nm EOT: thin gate dielectric, surface-channel device
5 nm quantum well thickness
<5 nm deep source / drain regions
~3 mA/mm target drive current low access resistance
self-aligned, low resisitivity source / drain contacts
self-aligned N+ source / drain regions with high doping
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22 nm InGaAs MOSFET: source resistance
LS/D
Id 
I di
1  g mi  Rs
Rs 
c
Wg LS / D

Lg
 sheet LS / D
2Wg
IBM High-k Metal gate transistor
Image Source:EE Times
• Source access resistance degrades Id and gm
• IC Package density : LS/D ~ Lg =22 nm c must be low
• Need low sheet resistance in thin ~5 nm N+ layer
• Design targets: c ~1 W-mm2, sheet ~ 400 W
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22nm ion implanted InGaAs MOSFET
Key Technological Challenges
• Shallow junctions ( ~ 5 nm), high (~5×1019 cm-3) doping
• Doping abruptness ( ~ 1 nm/decade)
• Lateral Straggle ( ~ 5 nm)
• Deep junctions would lead to degraded short channel effects
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InGaAs MOSFET with raised source/drain by regrowth
HAADF-STEM1*
InGaAs
regrowth
Interface
InGaAs
2 nm
* TEM by J. Cagnon, Susanne Stemmer Group, UCSB
Self-aligned source/drain defined by MBE regrowth1
Self-aligned in-situ Mo contacts2
Process flow & dimensions selected for 22 nm Lg design;
present devices @ 200 nm gate length
1Wistey,
EMC 2008
EMC 2009
2Baraskar,
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Regrown S/D process: key features
Self-aligned & low resistivity
...source / drain N+ regions
...source / drain metal contacts
Vertical S/D doping profile set by MBE
abrupt on ~ 1 nm scale
Gate-first
gate dielectric formed after MBE growth
uncontaminated / undamaged surface
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Process flow*
* Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
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Key challenge in S/D process: gate stack etch
Requirement: avoid damaging semiconductor surface:
Approach: Gate stack with multiple selective etches*
FIB Cross-section
SiO2
Damage free channel
Cr
W
Process scalable to sub-100 nm gate lengths
* Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
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Key challenge in S/D process: dielectric sidewall
Sidewall must be kept thin: avoid carrier depletion, source starvation.
• Target < 15 nm sidewall in 22 nm Lg device
• 20-25 nm SiNx thick sidewalls in present devices
• Pulse doping in the barrier: compensate for carrier depletion from Dit
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MOSFET SEMs
SiO2
SiNx
Cr
W
InGaAs
regrowth
W/Cr gate Pad
Original
interface
Cross-section after regrowth,
but before Mo deposition
Mo
+InGaAs
Ti/Au Pad
Top view of completed device
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MOSFET characteristics
4.7 nm Al203 , 1×1013 cm-2 pulse
doping
1
L =0.8mm, W
g
g
=0.5 V
0.6
ds
0.4
0
0
1
1.5
2
=0.5 V
gs_step
0.4
0.2
0.5
gs
0.6
0.2
0
=12mm
g,eff
V = -1 V to 3.5, V
0.8
gs_step
I (mA/mm)
ds
I (mA/mm)
gs
L =1.0mm, W
g,eff
V = -1 V to 3.5, V
0.8
1
=9mm
0
0.5
V (V)
ds
1
1.5
2
V (V)
ds
• Maximum Drive current (Id): 0.95 mA/mm
• Peak transconductance (gm): 0.37 mS/mm
Id and gm below expected values
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FET source resistance
7000
SEM
V =3.0 V
gs
6000
4000
3000
R
on
(W-mm)
5000
2000
R +R
1000
S
D
= 1.0 kW-mm
0
0
2
InGaAs regrowth on unprocessed thin InP*
4
6
Gate Length (mm)
8
10
• Series resistance estimated by extrapolating Ron to zero gate length
• Source access resistance ~ 500 W-mm
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Source resistance : regrowth TLMs
40
SEM
Resistance (W)
35
SEM
InGaAs
regrowth
W~ 20 mm
FET
30
25 / Cr / SiO2 gate
W
Regrowth TLMs
No regrowth
20
15
10
R
sh
5
~ 29 W
Rc ~ 5.5 W-mm (12.6 W-mm)
2
0
0
5
10
15
20
Contact Separation ( mm)
25
30
• TLMs fabricated on the regrowth far away from the gate
• Regrowth sheet resistance ~ 29 W
• Mo/InGaAs contact resistance ~ 5.5 W-mm2 (12.6 W-mm)
TLM data does not explain 500 W-mm observed FET source resistance
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Source resistance: electron depletion near gate
SiO2
InGaAs
regrowth
SiNx
Cr
W
Original
interface
R1
R2
• Electron depletion in regrowth shadow region (R1 )
• Electron depletion in the channel under SiNx sidewalls (R2 )
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InAs source/drain regrowth
Gate
InAs
regrowth
top of gate
side of gate
Mo S/D metal with
N+ InAs underneath
Improved InAs regrowth with low As flux for uniform filling1
InAs less susceptible to electron depletion: Fermi pinning above Ec2
1
Wistey et al, EMC 2009
Wistey et al NAMBE 2009.
2Bhargava et al , APL 1997
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Conclusion
• Self-aligned raised source/drain for scaled channel ( 5nm)
• D-FETs: peak Id = 0.95 mA/mm, and peak gm =0.37 mS/mm
• InAs Source/Drain E-FETs1
• Next:
scale to ~50 nm Lg
gate dielectric quality
This work was supported by Semiconductor Research Corporation under the
Non-classical CMOS Research Program
1Singisetti
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et al, EDL submitted
DRC 2009