Transcript Lecture 15 PicoBlaze I/O & Interrupt Interface ECE 448 – FPGA and ASIC Design with VHDL.

Lecture 15
PicoBlaze I/O & Interrupt Interface
ECE 448 – FPGA and ASIC Design with VHDL
Required reading
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 16, PicoBlaze I/O Interface
Chapter 17, PicoBlaze Interrupt Interface
ECE 448 – FPGA and ASIC Design with VHDL
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Syntax and Terminology
Syntax
Example
Definition
sX
s7
Value at register 7
KK
ab
Value ab (in hex)
PORT(KK)
PORT(2)
PORT((sX))
PORT((s1))
RAM(KK)
RAM(4)
Input value from port 2
Input value from the port specified by register s1
Value from the RAM location 4
Addressing modes
Immediate mode
SUB
s7, 07
ADDCY s2, 08
s7 – 07
 s7
s2 + 08 + C  s2
Direct mode
ADD
sa, sf
INPUT s5, 2a
sa + sf  sa
PORT(2a)  s5
Indirect mode
STORE s3, (sa)
s3  RAM((sa))
INPUT s9, (s2)
PORT((s2))  s9
Output Decoding of Four Output Registers
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Output Instructions
C Z
OUTPUT sX, KK
DIR
−−
IND
−−
PORT(KK) <= sX
OUTPUT sX, (sY)
PORT((sY)) <= sX
Timing Diagram of an Output Instruction
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Truth Table of a Decoding Circuit
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Input Instructions
C Z
INPUT sX, KK
DIR
−−
IND
−−
sX <= PORT(KK)
INPUT sX, (sY)
sX <= PORT((sY))
Block Diagram of Four Continuous-Access Ports
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Timing Diagram of an Input Instruction
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Block Diagram of Four Single-Access Ports
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FIFO Interface
clk
rst
clk
rst
FIFO
din
dout
8
8
full
write
empty
read
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Operation of the “Standard” FIFO
−−−−−
A
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C
D
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Operation of the First-Word Fall-Through FIFO
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Timing Diagram of an Input Instruction
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Interrupt
Flow
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Timing Diagram of an Interrupt Event
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Interrupt Related Instructions
RETURNI ENABLE
PC <= STACK[TOS] ; TOS <= TOS – 1;
I <= 1; C<= PRESERVED C; Z<= PRESERVED Z
RETURNI DISABLE
PC <= STACK[TOS] ; TOS <= TOS – 1;
I <= 0; C<= PRESERVED C; Z<= PRESERVED Z
ENABLE INTERRUPT
I <=1;
DISABLE INTERRUPT
I <=0;
Interrupt Interface with a Single Event
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Interrupt Interface with Two Requests
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