Transcript Princess Sumaya Univ. Computer Engineering Dept. Chapter 5: Princess Sumaya University 22343 – Computer Organization & Design Computer Engineering Dept. Stored Program Architecture  Instruction Cycle ● Fetch.

Princess Sumaya Univ.
Computer Engineering Dept.
Chapter 5:
Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Stored Program Architecture
 Instruction Cycle
● Fetch an instruction from memory
● Decode the instruction
Instructions
(Program)
Opcode
Operands
● Get the operands
● Execute the instruction
 Where is the next instruction?
Operands
(Data)
Binary Operand
Program Counter (PC)
Instruction Pointer (IP)
 Where is the operand?
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Princess Sumaya University
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Computer Engineering Dept.
CPU
 Datapath
 Control Unit
Register File
CU
ALU
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
General-Purpose Register Organization
Memory
& I/O
R1
R2
R3
R4
R5
R6
R7
ASEL
MUX
A
3x8
Decoder
OPR
DSEL
MUX
BSEL
B
ALU
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Computer Engineering Dept.
General-Purpose Register Organization
Memory
& I/O
R1
00000
00001
00010
00101
00110
01000
01010
01100
01110
10000
11000
R2
Transfer A
Increment A
Add A + B
Subtract A − B
Decrement A
AND A and B
OR A and B
XOR A and B
Complement A
Shift right A
Shift left A
Examples:
Operation
R1 ← R2 − R3
R4 ← SHL R4
R3
R4
R5
R6
R7
ASEL
MUX
A
3x8
Decoder
OPR
DSEL
OPR
ASEL
MUX
BSEL
BSEL
B
ALU
DSEL
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
General-Purpose Register Organization
00000
00001
00010
00101
00110
01000
01010
01100
01110
10000
11000
Transfer A
Increment A
Add A + B
Subtract A − B
Decrement A
AND A and B
OR A and B
XOR A and B
Complement A
Shift right A
Shift left A
Examples:
Operation
R1 ← R2 − R3
R4 ← SHL R4
Instructions
(Program)
00101 010 011 001 00
Operands
(Data)
0000 0000 0000 0000
OPR
00101
11000
ASEL
010
100
BSEL
011
000
DSEL
001
100
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Memory Interface
 Address / Data Buses
 Read / Write Control
 Bidirectional /
Unidirectional
Data Bus
Read
Write
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Building a Datapath
Write a program & compile it.
Where do you want to put it?
Where is the first instruction?
What comes out of memory?
Where to perform operation?
Where are the operands?
Who well tell us which reg?
Where to store result?
Can we save this reg to mem?
 Datapath Elements
Addr
Data
Instruction
Memory
Reg A Data
(Read) A
Reg B Data
(Read) B
32
32
ALU
PC
Register File
Reg C
(Write)
Data
C
32
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Computer Engineering Dept.
Building a Datapath
 Datapath Elements
Addr
Data
Instruction
Memory
Reg A Data
(Read) A
Reg B Data
(Read) B
ALU
PC
Register File
Addr Data
Reg C
(Write)
Data
Memory
Data
C
Data
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Computer Engineering Dept.
Building a Datapath
How can we read it back?
Addr
Data
Instruction
Memory
Reg A Data
(Read) A
Reg B Data
(Read) B
ALU
PC
Register File
Addr Data
Reg C
(Write)
Data
Memory
Data
C
Data
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Computer Engineering Dept.
Building a Datapath
Finished executing instruction.
Where is the next instruction?
Why +4?
Adder
4
Data
Instruction
Memory
Addr Data
Reg C
(Write)
Data
Memory
Data
C
Data
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MUX
Addr
Reg A Data
(Read) A
Reg B Data
(Read) B
ALU
PC
Register File
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Princess Sumaya University
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Computer Engineering Dept.
Building a Datapath
How can we add “immediate”?
What if it is 8-bit negative?
Adder
4
Data
Instruction
Memory
Addr Data
Reg C
(Write)
Data
Memory
Data
C
Data
MUX
Addr
Reg A Data
(Read) A
Reg B Data
(Read) B
ALU
PC
Register File
Sign
Extend
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Building a Datapath
What about “JMP Rel Disp”?
It can be positive or negative!
Adder
4
Instruction
Memory
Reg C
(Write)
Data
C
Addr Data
Data
Memory
Data
MUX
Data
ALU
Addr
Reg A Data
(Read) A
Reg B Data
(Read) B
MUX
PC
Register File
Sign
Extend
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Computer Engineering Dept.
Building a Datapath
Instruction
Memory
Reg C
(Write)
Data
C
Addr Data
Data
Memory
Data
MUX
Data
ALU
Addr
Reg A Data
(Read) A
Reg B Data
(Read) B
Shift
Left 2
MUX
PC
Register File
Adder
Adder
4
Sign
Extend
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Computer Engineering Dept.
Building a Datapath
Reg C
(Write)
Data
C
Addr Data
Data
Memory
Data
MUX
Instruction
Memory
ALU
Data
Adder
Adder
Addr
Reg A Data
(Read) A
Reg B Data
(Read) B
Shift
Left 2
MUX
PC
Register File
MUX
Why the shift?
4
Sign
Extend
Answer:
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Computer Engineering Dept.
Instruction
Memory
Reg C
(Write)
Data
C
Addr Data
Data
Memory
Data
MUX
Data
Why not use
ALU instead of
another adder?
ALU
Addr
Reg A Data
(Read) A
Reg B Data
(Read) B
Shift
Left 2
MUX
PC
Register File
Adder
Adder
4
MUX
Building a Datapath
Sign
Extend
Answer:
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Computer Engineering Dept.
Adding Control Signals to the Datapath
0
Addr
Data
Instruction
Opcode Memory
etc
Control
Unit
Reg A Data
(Read) A
Reg B Data
(Read) B
Reg C
(Write)
Data
C
Sign
Extend
Shift
Left 2
0
M
U
X
ALU
PC
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
1
Data
1
M
U
X
0
Cy, Z,
etc
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Princess Sumaya University
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Computer Engineering Dept.
Adding Control Signals to the Datapath
0
Addr
Data
Instruction
Memory
Control
Unit
Reg A Data
(Read) A
Reg B Data
(Read) B
Reg C
(Write)
Data
C
Shift
Left 2
0
M
U
X
1
ALU
PC
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
Data
1
M
U
X
0
Sign
Extend
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A Simple Implementation Scheme
 ALU Control
32
32
ALU Cntrl
Cy
Z
4
ALU
32
0000
0001
0010
0110
0111
1100
Cy = 1  Carry from last adder
Z = 1  The result = 0
AND
OR
Add
Subtract
Set on Less Than
NOR
slt
R1, R2, R3
1
R1  
0
if R2  R3
otherwise
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A Simple Implementation Scheme
 Instruction Format
Opcode
● Arithmetic/Logic
Rd = Rs Funct Rt
Operand(s), Address, Code
6
5
5
5
5
6
0
Rs
Rt
Rd
Shift
Funct
Funct
ALU Operation
ALU Cntrl Lines
100000
Add
0010
100010
Subtract
0110
100100
AND
0000
100101
OR
0001
101010
SLT
0111
Register File
Reg A Data
(Read) A
Reg B Data
(Read) B
Reg C
(Write)
Data
C
Example:
000000 00011 00111 00101 00000 100000
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Princess Sumaya University
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A Simple Implementation Scheme
 Instruction Format
● Load Immediate
Opcode
Operand(s), Address, Code
6
5
5
16
Lower Rt = Value
13
0
Rt
Immediate (Lower)
Upper Rt = Value
16
0
Rt
Immediate (Upper)
Example: R1 = 12
001101 00000 00001 0000 0000 0000 1100
010000 00000 00001 0000 0000 0000 0000
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
A Simple Implementation Scheme
 Instruction Format
● Load Memory
Rt = M [Rs + Addr]
32 bits
Opcode
Operand(s), Address, Code
6
5
5
16
35
Rs
Rt
Address
16 bits (can be positive or negative)
Example: R6 = M [R4 – 1 ]
100011 00100 00110 1111 1111 1111 1111
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A Simple Implementation Scheme
 Instruction Format
● Store Memory
M [Rs + Addr] = Rt
Opcode
Operand(s), Address, Code
6
5
5
16
43
Rs
Rt
Address
Example: M [R7 – 2 ] = R9
101011 00111 01001 1111 1111 1111 1110
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Computer Engineering Dept.
A Simple Implementation Scheme
 Instruction Format
● JE Operation
If Rs = Rt then
Opcode
Operand(s), Address, Code
6
5
5
16
4
Rs
Rt
Offset
PC = PC + 4*Addr
PC is already incremented
Example:
000100 00001 00100 1111 1111 1111 1111
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Final Datapath Design
0
PC
Rs
Addr
Data
Rt
Rt
M
Instruction Rd U
X
Memory
Reg A Data
(Read) A
Reg B Data
(Read) B
Reg C
(Write)
Data
C
Offset, Addr,
Immediate
Shift
Left 2
0
M
U
X
1
ALU
Register File
M
U
X
Adder
Adder
4
1
Addr Data
Data
Memory
Data
1
M
U
X
0
Sign
Extend
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Program Setup
 Write a Program
Example:
 Assemble it
 Store it in Memory
0 3401000A
001101 00000 00001 0000 0000 0000 1010
4 00210820
000000 00001 00001 00001 00000 100000
8 1021FFFF
000100 00001 00001 1111 1111 1111 1111
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Datapath Operation
 Fetch Instruction
 Decode Instruction
 Get Operands
Execute it
CLK
PC
I-Mem
Adder MUX
PC Adder
Reg ASel
Reg CSel
Reg CWrite
0
3401000A (LLI R1, 10)
ƮM
4
ƮAdder
0
1
ALU MUX
ALU Ctrl
Mem MUX
Data A
Sign Ext
ALU
Data C
2 (Add)
0
ƮReg
10
ƮALU
10
10
Rs
Rt
Immediate
13 0
1
10
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ƮReg
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Datapath Operation
 How Fast Can the
Clock Be?
Ʈclk
CLK
PC
I-Mem
Adder MUX
PC Adder
Reg ASel
Reg CSel
Reg CWrite
0
ƮM
3401000A (LLI R1, 10)
4
0
1
ALU MUX
ALU Ctrl
Mem MUX
Data A
Sign Ext
ALU
Data C
2 (Add)
0
ƮReg
10
10
ƮALU
ƮReg
6:35 AM
10
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Princess Sumaya University
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Computer Engineering Dept.
Datapath Operation
 Fetch Instruction
 Decode Instruction
 Get Operands
Execute it
CLK
PC
I-Mem
Adder MUX
PC Adder
Reg ASel
Reg CSel
Reg CWrite
0
4
00210820(Add R1,R1,R1)
8
4
0
1
1
1
ALU MUX
ALU Ctrl 2
2 (Add)
Mem MUX
Data A 0
Data B
ALU 10
Data C 10
0
10
10
20
20
Rs
Rt
Rd Shift
1
1
1
0
Funct
32
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Princess Sumaya University
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Datapath Operation
 Fetch Instruction
CLK
PC
I-Mem
 Decode Instruction
 Get Operands
Execute it
4
8
1021FFFF (JE R1,R1,-1)
12
PC Adder 8
PC Adder 2
Adder MUX
8
Reg ASel 1
Reg CSel 1
Reg CWrite
1
1
ALU MUX
ALU Ctrl 2
Data A 10
Data B 10
ALU 20
4
6 (Sub)
20
20
0
Rs
Rt
Offset
1
1
–1
6:35 AM
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Datapath Operation
 How Fast Can the
Clock Be?
CLK
PC
I-Mem
4
8
ƮM
1021FFFF (JE R1,R1,-1)
12
PC Adder 8
PC Adder 2
Adder MUX
8
Reg ASel 1
Reg CSel 1
Reg CWrite
ALU MUX
ALU Ctrl 2
Data A 10
Data B 10
ALU 20
1
1
6 (Sub)
20
ƮReg
20
ƮALU
6:35 AM
0
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Datapath Operation
 How Fast Can the
Clock Be?
Ʈclk
CLK
PC
I-Mem
4
PC Adder 8
PC Adder 2
Adder MUX
8
ƮM
1021FFFF (JE R1,R1,-1)
12
ƮAdder
Reg ASel 1
Reg CSel 1
Reg CWrite
ALU MUX
ALU Ctrl 2
Data A 10
Data B 10
ALU 20
8
ƮAdder
1
1
6 (Sub)
20
ƮReg
20
ƮALU
6:35 AM
0
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Computer Engineering Dept.
Single-Cycle Implementation
 Fetch Instruction
 Decode Instruction
 Get Operands
Execute it
CLK
PC
I-Mem
i
8C640007 (LD R4,[R3+7])
Reg ASel
Reg CSel
Reg CWrite
ALU MUX
ALU Ctrl
Mem MUX
Data A
Sign Ext
3
4
2 (Add)
d
7
ALU
d+7
v
D-Mem
Data C
v
Rs
Rt
Address
35 3
4
7
6:35 AM
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Princess Sumaya University
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Computer Engineering Dept.
Single-Cycle Implementation
 Clock Speed?
Ʈclk
CLK
PC
I-Mem
Reg ASel
Reg CSel
Reg CWrite
ALU MUX
ALU Ctrl
Mem MUX
Data A
Sign Ext
ALU
D-Mem
Data C
i
ƮM
8C640007 (LD R4,[R3+7])
3
4
2 (Add)
d
ƮReg
7
d+7
ƮALU
v
ƮM
v
ƮReg
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22343 – Computer Organization & Design
Computer Engineering Dept.
Single-Cycle Implementation
Example:
ƮM = 200 picoseconds
ƮALU = 100 picoseconds
ƮAdder = 100 picoseconds
ƮReg = 50 picoseconds
Delay
LI / ALU
400 ps
LD
600 ps
ST
550 ps
Cond. Jump
350 ps
Ʈclk =
ps 
Load Memory:
Ʈclk > 2 ƮM + 2 ƮReg + ƮALU
Store Memory:
Ʈclk > 2 ƮM + ƮReg + ƮALU
Fastest Clock?
Type
Load Immediate/ALU:
Ʈclk > ƮM + 2 ƮReg + ƮALU
Conditional Jump:
ƮM + ƮReg + ƮALU
Ʈclk > Max
2 ƮAdder
GHz
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Computer Engineering Dept.
Multicycle Implementation
 Instructions take different number of clock cycles
 Functional units can be shared within the
execution of a single instruction
Reg C
(Write) Data
B
Data
C
Result
X
ALU
Memory
Data Data
Reg A Data
(Read) A
Reg B
(Read)
Addr
MDR
PC
IR
Register File
Y
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Multicycle Implementation
 Some registers are not visible to the programmer
MDR
Memory
Reg C
(Write) Data
B
Data
C
Sign
Extend
4
Result
X
Reg B
(Read)
Addr
Data Data
Reg A Data
(Read) A
ALU
PC
IR
Register File
Y
Shift
Left
2
Exercise: Can you do all the previous instruction here?
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Multicycle Implementation
 Some registers are not visible to the programmer
Register File
X
Reg B
(Read)
Addr
0
1
Data
Data
0
1
0
1
Reg C
(Write) Data
B
Data
C
Sign
Extend
4
Y
ALU
0
1
MDR
0
1
PC
IR
Reg A Data
(Read) A
0
1
2
3
Result
Memory
Shift
Left
2
6:35 AM
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Multicycle Datapath Operation
 Fetch Instruction
Ʈclk
1
CLK
PC
0
MemRd
IRLD
IR
Mem Out
X MUX
Y MUX
ALU Ctrl
ALU
PC MUX
3401000A
ƮM
0
2 (Add)
ƮALU
4
PCLD
6:35 AM
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Multicycle Datapath Operation
 Fetch Instruction
CLK
PC
 Decode Instruction
MemRd
 Get Operands
Ʈclk
2
0
4
IRLD
IR
Mem Out
3401000A (LLI R1, 10)
Reg ASel
XLD
X
Data A
Sign Ext
0
0
ƮReg
10
Rs
Rt
Immediate
13 0
1
10
6:35 AM
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Multicycle Datapath Operation
 Fetch Instruction
 Decode Instruction
 Get Operands
Execute it
Ʈclk
CLK
PC
IR
XLD
X
X MUX
Y MUX
ALU Ctrl
ResultLD
3
4
3401000A (LLI R1, 10)
0
2
2 (Add)
Result
ALU
ƮALU
Rs
Rt
Immediate
13 0
1
10
10
6:35 AM
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Multicycle Datapath Operation
 Fetch Instruction
 Decode Instruction
 Get Operands
Execute it
Ʈclk
4
CLK
PC
IR
ResultLD
Result
Reg CSel
4
3401000A (LLI R1, 10)
10
1
C MUX
Reg CWrite
ƮReg
Ʈclk
Rs
Rt
Immediate
13 0
1
10
6:35 AM
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Multicycle Datapath Operation
CLK
PCLD
PC
MemRd
Mem Out
IRLD
IR
Reg ASel
Data A
XLD
X
Sign Ext
ALU Ctrl
ALU
ResultLD
Result
Reg CSel
Reg CWrite
0
13
Computer Engineering Dept.
Rs
Rt
Immediate
0
1
10
4
3401000A
3401000A (LLI R1, 10)
0
0
0
10
2 (Add)
2 (Add)
4
10
10
1
IR  M[PC]
PC  PC + 4
X  Reg[IR[25:21]] R  X+IR[15:0] Reg[IR[20:16]]  R
Rs
Immediate
Rt .
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Multicycle Datapath Operation
CLK
PCLD
PC
MemRd
Mem Out
IRLD
IR
Reg ASel
Data A
XLD
X
Sign Ext
ALU Ctrl
ALU
ResultLD
Result
Reg CSel
Reg CWrite
i
i+4
instruction
instruction
Rs Selection
Rs
Rs
value
Add
Add
i+4
i+4+disp
Opcode
result
i+4+disp
result
Rd
IR  M[PC]
PC  PC + 4
Rt
X  Reg[IR[25:21]] ALU Operation:
Reg[IR[15,11]]  R LD Operation:
R

X
op
Y
Y  Reg[IR[20:16]]
MDR  Mem[R] Reg[IR[20:16]]  MDR.
R  PC+IR[16:0]] R  X op IR[16:0]
Mem[R]  Y
Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Multicycle Implementation
Example:
ƮM = 200 picoseconds
ƮALU = 100 picoseconds
ƮAdder = 100 picoseconds
ƮReg = 50 picoseconds
Fastest Clock?
Type
Instr. Mix
LI / ALU
52%
LD
25%
ST
10%
Cond. Jump
13%
Ʈclk =

Load Immediate/ALU:
4 Clocks
Load Memory:
5 Clocks
Store Memory:
4 Clocks
Conditional Jump:
3 Clocks
On Average:
CPI =
Instr. Exec. Time =
GHz
6:35 AM
ps
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Control Implementation
Datapath Control Signals:
ALU Operation, MUX Selection,
Memory Rd/Wr, etc
•••
Data Processing Unit
DPU or Datapath
CU
•••
Control Unit
Datapath Status Signals:
IR Fields, ALU Flags
6:35 AM
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Control Implementation
 Hardwired
● Standard Logic Components
● Fast
● Not Flexible, i.e. Difficult to Change Control Operation
 Microprogrammed
● Memory-Based
● Speed Function of Memory (slower than hardwired)
● Flexible Design
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Control Implementation
Combinational
Control
Logic
Datapath
Control
Outputs
•••
● Finite
State
Machine
•••
 Hardwired
•••
Datapath
Control
inputs
State Register
•••
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Microprogrammed Control Implementation
 Each Line
in the MicroProgram
Executes
MicroOperations
(in 1 Clock)
 Fetch,
Decode,
Execute
Cycle
Microprogram
Counter
Microprogram
Memory
(Microstore)
ALU Operation, MUX Selection,
Memory Rd/Wr, etc
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Microprogram Control Unit
Datapath Control Signals:
C19
PC MUX
Selects ALU or Result
C18
PC Load
PC loads a new value
C17
Mem MUX
Selects Result or PC
C16
Mem RD
Memory read operation
C15
Mem WR
Memory write operation
C14
IR LD
IR loads a new value
C6
Y MUX1
C13
MDR LD
MDR loads a new value
C5
Y MUX0
C12
RegC MUX
Selects Rt or Rd fields
C4
ALU3
C11
DataC MUX
Selects MDR or Result
C3
ALU2
C10
Reg WR
Register write operation
C2
ALU1
C9
X LD
X loads a new value
C1
ALU0
C8
Y LD
Y Loads a new value
C0
R LD
C7
X MUX
Selects PC or X
Selects ‘4’, Y, Sign Ext
or Shift Left 2
Selects ALU operation
Result loads a new value
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Microprogram Control Unit
Opcode
IR
Funct
M
A
P
MUX
Adder
Z
Cy
etc
μPC
Condition
Select
1
μProgram Memory
C19
C0
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Microprogram Control Unit
 Fetch Instruction
IR  M[PC]
PC  PC + 4
μPC
M 0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
0
1
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Microprogram Control Unit
 Decode / Get Operands
IR  M[PC]
PC  PC + 4
X  Reg[IR[25:21]]
Y  Reg[IR[20:16]]
R  PC+4*IR[15:0]]
μPC
M 0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 1
1
0 0 0 0 0 1 0
=8
Opcode = 0
Funct = 100010
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Microprogram Control Unit
 Execute Instruction
IR  M[PC]
PC  PC + 4
X  Reg[IR[25:21]]
Y  Reg[IR[20:16]]
R  PC+4*IR[15:0]]
RX– Y
μPC
M 0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 1
1
1 0 0
=8
Opcode = 0
Funct = 100010
0 0 0 0 0 1 0
1 1 0 1 1 0 0 1 0 1
8
9
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Princess Sumaya University
22343 – Computer Organization & Design
Computer Engineering Dept.
Microprogram Control Unit
 Execute Instruction
IR  M[PC]
PC  PC + 4
X  Reg[IR[25:21]]
Y  Reg[IR[20:16]]
R  PC+4*IR[15:0]]
RX– Y
Reg[IR[15,11]]  R
μPC
M 0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 1
1
1 0 0
=8
Opcode = 0
Funct = 100010
8 0 0 1 0 0 1 0 0 1
9
0 0 0 0 0 1 0
1 1 0 1 1 0 0 1 0 1
1 0 1 0 1 1 0 1
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Princess Sumaya University
Chapter 5
22343 – Computer Organization & Design
Computer Engineering Dept.