Transcript Introduction to Bus Organization

Introduction to Bus Organization
• Point-to-point wiring: Every functional block in our system is uniquely wired to
every other functional block in the system
Complex
Functional Block #1
I/O Interface
Complex
Functional Block #2
I/O Interface
Complex
Functional Block #3
I/O Interface
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
I/O Interface
Complex
Functional Block #4
I/O Interface
Complex
Functional Block #5
I/O Interface
Complex
Functional Block #6
Hardware Computer Organization for the Software Professional
Arnold S. Berger
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Introduction to Bus Organization
Complex
Functional Block #1
IN
CONTROL
I/O Interface
INPUT DECISION LOGIC
In from
#2
In from
#3
In from
#4
In from
#5
OUT
CONTROL
OUTPUT DECISION LOGIC
In from
#6
Out to
#2
Out to
#3
Out to
#4
Out to
#5
Single bit inputs from other blocks
Single bit outputs to other blocks
Hardware Computer Organization for the Software Professional
Arnold S. Berger
Out to
#6
2
Bus organization
Complex
Functional Block #1
I/O Interface
I/O Interface
IN/OUT
IN/OUT
How do we manage the
flow of information?
Complex
Functional Block #2
Complex
Functional Block #3
I/O Interface
IN/OUT
OUTPUT
=0
OUTPUT 0 > 1
IN/OUT
I/O Interface
Complex
Functional Block #4
IN/OUT
I/O Interface
Complex
Functional Block #5
IN/OUT
I/O Interface
Complex
Functional Block #6
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Bus organization
•
•
Busses were invented in order to simplify the organization and flow of data
within computer systems
- Busses allow many devices to connect to the the same data path
- Allow for efficient exchange of data between devices
Question: How do I connect outputs together and not get a short circuit?
BUS
1
1
AND
Gate 1
1 (5V)
0 (0V)
AND
Gate 2
1
0
Short circuit ( bus contention)
Actual result will be an indeterminate logic level
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Bus organization(2)
•
Answer: All logic devices that connect to a bus are actually divided into two
parts: Logic functional block and bus interface unit
Bus
Interface
Input
Logic
Function
Bus control
• Close the switch > output connected
• Open the switch > output disconnected
Hardware Computer Organization for the Software Professional
Arnold S. Berger
BUS
5
8-bit Data Bus
DB0
DB1
DB2
Connection
Symbol
DB3
DB4
DB5
DB6
DB7
Bus
Interface
CE
Actual
Logic inputs
DB7
DB6
DB5
DB4
DB3
DB2
DB1
Hardware Computer Organization for the Software Professional
Arnold S. Berger
DB0
6
Tristate bus organization
Data Bus D0..D31
D31
CS0
D31
CS1
D0
32-bit register
D0
D0
32-bit register
D0
32-bit register
•
With a tristated bus, outputs can be connected directly to the bus, but the
chip select signals must be controlled through appropriate addressing
Suggested exercise: Derive the Truth Table for a 2:4 decoder
32-bit register
•
D31
CS2
2:4 Address Decoder
A0
A1
D31
CS3
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Algorithmic State Machine Revisited
DATA BUS
Register A
Temporary
Register
Register B
Arithmetic and logic unit (ALU)
clk_A
oe_A
clk_B
oe_B
clk_t
ALU_0
ALU_1
ALU_2
Microsequence Controller
ALU Output
Register
C
oe_OUT
clk_OUT
System Clock in
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Why do we need an ASM?
clk_A
oe_A
clk_B
oe_B
clk_T
clk_OUT
oe_OUT
ALU_0
ALU_1
ALU_2
clk_A
oe_A
clk_B
oe_B
clk_T
clk_OUT
oe_OUT
ALU_0
ALU_1
ALU_2
•
Bus organization simplifies data routing
ASM provides mechanism for sequencing multiple operands on the internal
busses of the processor
Question: What might the state transition table for the addition operation
look like for the operation <reg A> + <reg B>
<reg A>?
clock
•
•
1
0
1
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
0
0
0
2
1
1
0
1
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
0
3
0
1
1
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
4
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
0
5
0
1
0
0
1
0
1
0
0
0
0
1
0
0
0
1
1
0
0
0
6
0
1
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
7
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
8
1
1
0
1
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
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A “D” flip-flop memory cell
A single bit memory cell
DATA I/O
Q
D
W
CLK
Flip-flop core
Without S,R and Q
OE
Tri-state buffer
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Memory organization
DB0
DB1
DB2
DB3
A0
D
A1
CS
R/W
Memory decoding logic
CLK
Q
OE
D
CLK
Q
D
OE
CLK
Q
D
Q
OE
D
CLK
Q
OE
(W0)D0..D3
(OE0)D0..D3
D
CLK
Q
OE
D
CLK
OE
CLK
Q
OE
D
CLK
Q
OE
(W1)D0..D3
(OE1)D0..D3
D
CLK
(W2)D0..D3
Q
OE
D
CLK
Q
D
OE
CLK
Q
D
Q
OE
D
CLK
Q
OE
(OE2)D0..D3
D
CLK
Q
OE
D
CLK
OE
CLK
Q
OE
D
CLK
Q
OE
(W3)D0..D3
(OE3)D0..D3
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Paging
•
•
•
•
Can create larger memory arrays but is difficult to manage across page
boundaries
- Generally not supported by commercial compilers
Useful for programs designed with overlays
Similar to how virtual memory is handled by operating systems
Example: Suppose that you have a processor with a 20-bit (220) addressing
range and you are using memories with 64K addressing
A15-A0
64K
Page
0
uP
CS
0000
A19-A16
64K
Page
1
64K
Page
E
64K
Page
F
CS
CS
CS
0001
1110
1111
Page select (4 to 16 decoder)
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Page size options
•
•
•
Paging is the fundamental method of organizing memory in computer
systems
In the previous example, we organized a 1 Mbyte memory space (20-bit )
as 16, 64Kbyte pages
We could have represented the address in many other ways:
Page address
Offset address bits
Page address bits
Page offset
NONE
NONE
0 to 1,048,575
A0 to A19
0 to 1
A19
0 to 524,287
A0 to A18
0 to 3
A19-A18
0 to 262,143
A0 to A17
0 to 7
A19-A17
0 to 131,071
A0 to A16
0 to 15
A19-A16
0 to 65,535
A0 to A15
0 to 31
A19-A15
0 to 32,767
A0 to A14
0 to 63
A19-A14
0 to 16,383
A0 to A13
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Linear address
Our example
13
Decoding the memory space
•
Design the SRAM memory system using 256-Kbit ( 32K x 8 ) SRAM chips
Address Bus: A0..A14
To uP
W
A15..A23
ADDR VAL
RD
WR
To uP
ADDRESS DECODE LOGIC
OE
A0 W
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
D0
D1
D2
D3
D4
D5
D6
D7
OE CE
CE0
CE1
A0 W
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
D0
D1
D2
D3
D4
D5
D6
D7
A0 W D0
A1
D1
A2
A3
A4
D2
A5
A6
D3
A7
A8
D4
A9
A10
D5
A11
A12
D6
A13
A14
D7
OE CE
A0 W D0
A1
D1
A2
A3
A4
D2
A5
A6
D3
A7
A8
D4
A9
A10
D5
A11
A12
D6
A13
A14
D7
OE CE
OE CE
Data Bus: D0..D15
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Expanding memory by width
D0 D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
A0 W D0
A1
D1
A2
A3
A4
D2
A5
A6
D3
A7
A8
D4
A9
A10
D5
A11
A12
D6
A13
A14
D7
OE CE
A0 W
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
D0
D1
D2
D3
D4
D5
D6
D7
OE CE
16-bit data bus, D0..D15
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Memory decoding
•
•
Suppose that our page size is 32K (214 )
When A15 through A23 = 1 AND the processor asserts that the address is
valid, then the highest 32K page of memory will be enabled
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Notes about DRAM memory
•
•
•
Reading and writing to a memory location causes the capacitor to be
recharged ( refreshed )
But how do you read or write to all the memory cells in enough time ( ~10
milliseconds ) in order to guarantee that no data is lost?
Solution: You “sort of read” a group of cells at a time
13 Column Address
Lines CA0..CA12
(0,0)
EXAMPLE:
A 64-Mbit DRAM
(0,1)
(0,8191)
(1,0)
13 Row Address
Lines RA0..RA12
(8191,0)
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(8191,8191)
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Microprocessor component systems
•
Three major busses of a microprocessor
- Address bus: Unidirectional
- Data bus: Bidirectional
- Status bus: Heterogeneous, additional control and housekeeping
signals
A1..A23
Status Bus
• RESET
• INTERRUPT
• BUS REQUEST
• BUS ACKNOWLEDGE
• CLOCK IN/OUT
• READ/WRITE
• BYTE WRITE SELECTORS
D0..D15
MC68000
Address Bus:
Out to Memory
16 Mbyte address space or
8 M words
Data Bus:
Out to Memory
Input from Memory
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Microprocessor timing
•
These are the gory details of a typical bus cycle
Memory Read Cycle
T1
T2
Memory Write Cycle
T3
T1
T2
T3
CLK
ADDRESS A0..AN
Address Valid
Address Valid
ADDR VAL
RD
WR
DATA D0..DN
Data
Valid
Data
Valid
WAIT
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Direct Memory Access (2)
•
In its simplest form, there is a handshake process between the processor and the
peripheral device
- Peripheral device requests control of the bus from the processor
- BUS REQUEST (BUSREQ)
- When processor completes present instruction cycle and no higher level
interrupts are pending, it sends out a BUS GRANT (BUSGRA), giving the
requesting device permission to begin its own memory cycles
- Processor then idles until BUSREQ signal goes away
Address, Data and Status Busses
BUSREQ
uP
MEMORY
ARRAY
PERIPHERAL
DEVICE
BUSGRA
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