Transcript Document

ΗΜΥ 100: Εισαγωγή στην Τεχνολογία
Διάλεξη 18
Εισαγωγή στα Ψηφιακά Συστήματα: Μέρος Δ
10 Νοεμβρίου, 2003
Μαρία Κ. Μιχαήλ, Ph.D.
Λέκτορας
TΜΗΜΑ ΗΛΕΚΤΡΟΛΟΓΩΝ ΜΗΧΑΝΙΚΩΝ ΚΑΙ ΜΗΧΑΝΙΚΩΝ
ΥΠΟΛΟΓΙΣΤΩΝ
ΠΟΛΥΤΕΧΝΙΚΗ ΣΧΟΛΗ
ΠΑΝΕΠΙΣΤΗΜΙΟ ΚΥΠΡΟΥ
Περίληψη

Combinational Binary Addition
n-bit addition
 Full Adder
 n-bit Adder


Sequential Circuits
Storage elements
 Sequential n-bit Adder


Computer Design

From transistor to computer
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Δυαδικός Ημιαθροιστής


S = (Χ  Υ’) + (Χ’  Υ) = Χ  Υ
C=ΧΥ
Μπλοκ Διάγραμμα
Υ
Χ
C
Λογικό Διάγραμμα
1 bit
Ημιαθροιστής
S
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n-bit Addition


Design an n-bit binary adder which performs
the addition of two n-bit binary numbers and
generates a n-bit sum and a carry out.
Example: Let n=4
Cout

C3 C2 C1 Cin
A3 A2 A1 A0
+B3 B2 B1 B0
-------------S3 S2 S 1 S0
1 1 0 1 0
1 1 0 1
+1 1 0 1
---------1 0 1 0
This requires 3-bit addition!
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Full Adder

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Full adder (for higher-order bit addition)
Combinational circuit that performs the
additions of 3 bits (two bits and a carryin bit)
Ai
Ci+1
Bi
1 bit
full adder
Ci
Block diagram
of a Full Adder
Si
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Full Adder (cont.)
Boolean
Ci+1 = AiBi + AiCi + BiCi



equations:
Ci+1 is 1 if at least two out of the three inputs are 1
Si = AiBi’ Ci’ + Ai’Bi’Ci + Ai’BiCi’ + AiBiCi
= Ai  Bi  Ci

Si is 1 if an odd number of the three inputs are 1
can design full adder circuit directly from
the above equations (requires 3 ANDs and 1 OR
for Ci+1 and 2 XORs for Si)
Can we do better?
You
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Full Adder using 2 Half Adders


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A full adder can also be realized with two half adders
and an OR gate, since Ci+1 can also be expressed as:
Ci+1 = AiBi + (Ai  Bi)Ci
Si = Ai  Bi  Ci
A logic diagram of a Full Adder
Ai
Si
Bi
Ci+1
Ci
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n-bit Combinational Adders


Perform parallel multi-bit addition
Ripple Carry Adder
Constructed using n 1-bit full adder blocks
in parallel.
 Cascade the full adders so that the carry
out from one becomes the carry in to the
next higher bit position.
 Simple design
 Time consuming. Why? (you’ll see in a bit!)

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Example: 4-bit Ripple Carry Adder
C4
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C3 C2 C1 C0
A3 A2 A1 A0
+B3 B2 B1 B0
-------------S3 S2 S1 S0
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Ripple Carry Adder Delay


Circuit delay in an n-bit ripple carry adder is
determined by the delay on the carry path from the
LSB (C0) to the MSB (Cn).
Let the delay in a 1-bit FA be Δ. Then, the delay of an
n-bit ripple carry adder is nΔ.
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Sequential Circuits

Combinational Logic:
Output depends only on current input
 Able to perform useful operations
(add/subtract/multiply/…)
 Require cascading of many structures
 Costly and inflexible

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Sequential Circuits (cont.)

Sequential Logic:
Output depends not only on current input
but also on past input values
 Store information between operations (no
need for cascading)
 Need some type of memory to remember
the past input values

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Sequential Circuits (cont.)
Circuits that we
have learned
so far
Information Storing
Circuits
Timed “States”
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Sequential Logic: Concept



Sequential Logic circuits remember past
inputs and past circuit state.
Outputs from the system are
“fed back” as new inputs (usually with
delay).
The storage elements are circuits that
are capable of storing binary
information: memory.
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Synchronous Sequential Circuits:
Flip flops as state memory
The flip-flops receive their inputs from the
combinational circuit and also from a clock signal
with pulses that occur at fixed intervals of time,
as shown in the timing diagram.

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Storing Elements
Can’t change the stored value!
Inverters
Buffers
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SR latch (NOR version)
-- SR: “set-reset”, bistable element with two extra
inputs; note the “undefined” output for S=R=1.
-- Reading the logic:

Q = (R+Q’)’ and Q’ = (S+Q)’
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R=S=1 ??

Undefined output, because
When S=R=1, both outputs go to zero.
 If both inputs now go to 0, the state of
the SR flip flop is depends on which input
remains a 1 longer before making transition
to 0.
 Hence, “undefined” state. MUST be
avoided.

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D Latch


One way to eliminate the undesirable
indeterminate state in the RS flip flop is to
ensure that inputs S and R are never 1
simultaneously. This is done in the D latch:
Observe that this is a NAND-implementation of the
SR-latch
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Sequential Binary Addition

How can we add two n-bit binary
numbers using ONLY one full adder and
a 1-bit storage element?
Ai
Ci+1
Bi
1 bit
full adder
Ci
Q
1 bit
Memory
D
Clock
Si
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Serial vs. Parallel Addition

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The parallel adder is a combinational circuit, whereas
the serial adder is a sequential circuit.
The parallel adder has n full adders for n-bit
operands, whereas the serial adder requires only one
full adder.
The serial circuit takes n clock cycles to complete an
addition.
In summary, the parallel adder in space is n times
larger than the serial adder, but it is n times faster.
The serial adder, although it is n times slower, is n
times smaller in space.
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Computer Design

Where/How do we start? Which
materials, how to proceed in the design
process, how to integrate very large
components, etc ?
 Most
basic electrical components
 Transistor
 Design
process: Bottom-up or Up-down ?
 Integration: parts, processes, human
knowledge
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Logic Circuits
X
Y
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The Vacuum Tube
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Bell Labs Museum
The First
Point-Contact
Transistor
1947
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Bell Labs
The First
Junction
Transistor
1951
M1752
Outside the Lab
Lab model
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Logic Circuits - Functions
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Latches and Flip-Flops
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Central Processing Unit (CPU)
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Basic Computer Structure
Stores programs,
I/O data, and
intermediate data
Supervises the
flow of info.
among all units
Performs arithmetic
and other dataprocessing operations
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Texas Instrument’s First IC -- 1958
Jack Kilby
Robert Noyce
Fairchild
Intel
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Originally with Transistors
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A Close Up Then
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Processors Now
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A Close Up Now
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