Transcript Chapter 8

Chapter 8 -- Analysis and Synthesis of
Synchronous Sequential Circuits
The Synchronous Sequential Circuit Model
Combinational
logic
xn
y1
...
zm
Yr
yr
Memory
Clock
Figure 8.1
z1
...
...
x1
...
Y1
Mealy Machine Model
A
1/1
0/0
B
1/0
0/1
0/0
1/0
C
X/Z
(a)
Input x
Present
0
1
state
A
B/1
C/0
B
B/0
A/1
C
A/0
C/0
Next state/output
(b)
Figure 8.2
Mealy Machine Timing Diagram -- Example 8.1
A
1/1
0/0
B
1/0
0/1
0/0
1/0
C
X/Z
T0
(a)
Input x
Present
0
1
state
A
B/1
C/0
B
B/0
A/1
C
A/0
C/0
T1
T2
T3
T4
T5
Clock
A
B
A
C
Input x
0
1
1
0
1
0
Output z
1
1
0
0
0
0
State
Next state/output
(b)
Figure 8.3
A
C
A
Moore Machine Model
0
1
W/0
X/1
0 0
1
1
Y/0
(a)
Present
state
W
X
Y
Input x
0
1 Outputs
Y X
0
X Y
1
X W
0
(b)
Figure 8.4
Moore Machine Timing Diagram -- Example 8.2
0
1
W/0
X/1
0 0
1
1
Y/0
(a)
Present
state
W
X
Y
Input x
0
1 Outputs
Y X
0
X Y
1
X W
0
(b)
T0
Clock
State
Input x
Output z
W
0
0
T1
T2
T3
T4
T5
Y
W
X
X
Y
1
0
1
0
0
1
0
1
1
0
Figure 8.5
X
Analysis of Sequential Circuit State Diagrams -Example 8.3
x/z
0/0
1/0
1/0
00
1/1
0/0
01
0/0
Figure 8.6
11
Timing Diagram for Example 8.3
x/z
0/0
1/0
1/0
1/1
0/0
00
01
11
0/0
Clock
x
0
0
1
0
1
0
0
1
1
0
0
0
1
0
y1
0
0
1
1
1
0
y2
0
0
0
1
1
1
1
1
1
z
0
0
0
0
0
0
1
1
0
Figure 8.7
0
0
Analysis of Sequential Circuit Logic Diagrams
Combinational logic
z
x
y
y
Q
D
Q
C
Y
Clock
Memory
(a)
Dt
D
C
Figure 8.8
Combinational logic
z
Timing Diagram for Figure 8.8 (a)
x
y
Clock
y
x
0
1
1
0
1
0
0
0
y
0
0
1
0
0
1
1
1
Q
D
Q
C
Y
Clock
Memory
(a)
Dt
D
Y=D
z
0
0
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
2
3
4
5
6
Glitch
Figure 8.9
7

C
Q
8
Q
0
t/Dt
1
2
3
(b)
4 t/Dt
State Table and State Diagram for Figure 8.8 (a)
Input xk
Present
0
1
state
Input xk
Present 0 0
1
state yk
0
1
k
y
Input xk
Input xk
Present
Present
0
1
0
1
state
state
Input xk
Input xk
00 0/01 1/0Present
A 1A/0 B/0
Present
0
state
state
yk
0 0/0 1/0
A A/0 B/0
1 1/0 0/1
B B/0 A/1
k
y
1
1
1/0 0/1
Next
state/output
(b)
Next state/output
(a)
(a)
0/0
0/0
A
(b) x/
x/ z
z 1/0
A1/0
B
1/1
1/1
(d)
(d)
Figure 8.10
B
B/0
A/1
Next
state/output
(c)
Next state/output
(c)
0/0
0/0
B
K-Maps for Circuit of Figure 8.8 (a)
xk
0
xk
0
1
0
1
yk
0
1
0
0
0
1
0
1
Input xk
Present
0
1
state
A A/0 B/0
yk
1
1
0
(a)
(b)
Figure 8.11
B
B/0
A/1
yk + 1/zk
(c)
Synchronous Sequential Circuit with T Flip-Flop -Example 8.4
z
x
y
y
Figure 8.12
Q
Q
T
C
Clock
Timing Diagram for Example 8.4
Clock
x
0
1
1
0
1
0
0
0
y
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
0
1
2
3
4
5
6
7
8
T
z
0
Figure 8.13
State Table and State Diagram for Example 8.4
xk
xk
0
yk
1
xk
yk 0
1
0
1
yk + 1/zk
0
1
1/0
0/0
1/0
0/1
Present
state
yk + 1/zk
(a)
A
B/0
A/0
B
B/0
A/1
(c)
x/
z
0/0
A
1
Next state/output
(b)
1/0
0
B
1/1
(d)
Figure 8.14
0/0
K-Maps for Example 8.4
xk
0
xk
0
1
0
0
k
0
xk
0
1
1
0
k
y
0
0
1*
0
1
1
0*
y
1
1
1
k
y
1
0
0
1
zk
Tk
yk + 1
(a)
(b)
(c)
xk
0
1
0
1/0
0/0
1
1/0
0/1
yk
yk + 1/zk
(d)
Figure 8.15
Synchronous Sequential Circuit with JK Flip-flops -Example 8.5
z
J1
Q
y1
C
K1
Q
J2
Q
y2
Q
y2
y1
x
C
K2
Clock
Figure 8.16
Timing Diagram and State Table for Example 8.5
C
x
0
0
1
1
1
1
0 0
y1
1
0
0
0
1
1
1 0
y2
0
0
0
1
0
1
1 0
0
0
0
0
0
1
0 0
J1 = xy2
K1 = x
J2 = x
K2 = x + y1
z = xy1 y2
(a)
x
y1 y2
0
1
00 00/0 01/0
01 00/0 10/0
11 00/0 11/1
10 00/0 11/0
(b)
Figure 8.17
K-Maps for Example 8.5
x
y1 y2
x
0
1
00
0
0
01
0
11
10
y1 y2
0
1
00
1
0
1
01
1
0
0
1
11
1
0
0
0
10
1
0
J1
K1
x
y1 y2
x
0
1
00
0
1
01
0
11
10
y1 y2
x
0
1
00
1
1
1
01
1
0
1
11
0
1
10
J2
y1 y2
0
1
00
0
0
1
01
0
0
1
0
11
0
1
1
0
10
0
0
K2
Figure 8.18
z
Generating the State Table From K-maps -Example 8.5
x
y 1 y2
00
01
0
01
01
1
01
01
00
10
11
11
11
01
01
10
10
10
01
01
00
10
J1 K1 J2 K2 J1 K1 J2 K2
(a)
y1 y 2
x
y 1 y2
x
0
1
00
00
01
00
00/0 01/0
01
00
10
01
00/0 10/0
11
00
11
11
00/0 11/1
10
00
11
10
00/0 11/0
Y1 Y2
(b)
Figure 8.19
0
1
Y1 Y2/z
(c)
Synchronous Sequential Circuit Synthesis
x
A
1/0
1/1
B
1/0
0/0
1/0
0/0
0/0
D
0/0
C
0
1
A
D/0
B/0
B
D/0
C/0
C
D/0
B/0
D
D/0
A/1
(a) Completely specified circuit
x
1/1
A
0/-
0/1/C
B
0
1
A
B/-
-/1
B
B/0
C/1
C
A/-
A/-
0/0
1/1
(b) Incompletely specified circuit
Figure 8.20
x
Introductory Synthesis Example -- Example 8.6
x
y1 y 2
State
x
0
1
A
A/0
B/0
A
0 0
00
00/0 01/0
B
A/0
C/1
B
0 1
01
00/0 11/1
C
B/0
D/0
C
1 1
11
01/0 10/0
D
C/1
D/0
D
1 0
10
11/1 10/0
y1 y2
00
0
x
1
0
0
y1 y2
0
00
0
1
0
0
1
Y1 Y2/z
(c)Transition
table
(b) State
assignment
(a) State table
x
y1 y2
y1 y2
x
00
0
0
1
1
01
0
1
01
0
1
11
0
0
11
0
1
11
1
0
1
0
10
1
1
10
1
0
(d) Output K-map
D1 (= Y1)
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
y1
(a) D flip-flop
y1
0
z
St
trans
Q(t)
0
1
01
10
State
Required
transitions
inputs
Q(t) Q(t + e)
D(t)
D2 (= Y2)
(e) Excitation K-maps
State
Required
transitions
inputs
Q(t) Q(t + e)
T(t)
0
0
0
0
1
1
1
0
1
1
1
0
(c) Clocked T flip-flop
Figure 8.21
Q
QSt
trans
Q(t)
0
y2 0
Q
y2 1
1Q
(d)
(f) L
x
z
x
y2
0
1
00
00/0 01/0
01
00/0 11/1
11
01/0 10/0
10
11/1 10/0
Y1 Y2/z
(c)Transition
table
y2
x
00
0
1
0
1
y1
01
0
1
11
1
0
10
y1
1
0
D2 (= Y2)
on K-maps
y2
y2
Q
D1
Q
C
Q
D2
Q
C
(f) Logic diagram
Clock
Flip-flop Input Tables -- Example 8.6
State
Required
transitions
inputs
Q(t) Q(t + e)
D(t)
State
transitions
Q(t) Q(t + e)
Required
inputs
S(t)
R(t)
0
0
0
0
0
0
d
0
1
1
0
1
1
0
1
0
0
1
0
0
1
1
1
1
1
1
d
0
(a) D flip-flop
(b) Clocked SR
State
Required
transitions
inputs
Q(t) Q(t + e)
T(t)
State
transitions
Q(t) Q(t + e)
Required
inputs
J(t)
K(t)
0
0
0
0
0
0
d
0
1
1
0
1
1
d
1
0
1
1
0
d
1
1
1
0
1
1
d
0
(c) Clocked T flip-flop
(d) Clocked JK flip-flop
Figure 8.22
Generating the JK Flip-flop Excitation Maps -Example 8.7
x
y1 y2
0
y1 y2
1
00 00/0 01/0
01
00/0 Required
11/1
State
transitions
inputs
11
01/0
10/0
Q(t) Q(t + e)
D(t)
State
transitions
Q(t) Q(t + e)
0
0
0
10 11/1
10/0
0
1
1
0
1
1
1
Y1 Y20/z
1
(a) Transition table
1
0
y1 y2
0
0
0
0
1
1
0
1
1
1
0
x
1
00
(c) Clocked T flip-flop
1
01
0
1
00 0d
1
0d
00 0d
1d
01 0d
1d
01 d1
d0
d1
d0
11 d0
d1
10d d0
d0
10 1d
0d
Required
inputs
S(t) 11
R(t)
0
0
0
1
1
1
0
0
1
1
1
d
0
0
J1K1
0
Required
inputs
J(t)
K(t)
00
0
1
1
0
1
d
1
0
d
1
d
0
d1
d
1
d
J2K2
(b) Excitation table
(b) Clocked SR
State
transitions
Q(t) Q(t + e)
y 1 y2
x
0
0
(a) D flip-flop
State
Required
transitions
inputs
Q(t) Q(t + e)
T(t)
x
y1 y2
x
y1 y 2
0
1
00
0
1
Figure
8.23
0
01
d
d
0
(d) Clocked JK flip-flop
d
d
Generating the JK Flip-flop Excitation Maps -Example 8.7
y1 y2
x
0
y1 y2
1
x
0
1
00 00/0 01/0
00 0d
01 00/0 11/1
1
0d
00 0d
1d
01 0d
1d
01 d1
d0
11 01/0 10/0
11 d1
d0
11 d0
d1
10 11/1 10/0
10 d0
d0
10 1d
0d
J1K1
(a) Transition table
x
0
1
00
0
0
01
0
11
10
y1 y2
x
1
00
d
d
1
01
d
d
d
11
d
d
10
Figure 8.23
J2K2
(b) Excitation table
0
J1
x
0
Y1 Y2/z
y1 y2
y 1 y2
y1 y2
x
0
1
00
0
1
d
01
d
1
0
11
0
0
10
K1
x
0
1
00
d
d
d
01
1
0
d
d
11
0
1
1
0
10
d
d
J2
(c) Excitation maps
y1 y 2
K2
Clocked JK Flip-Flop Implementation -Example 8.7
x
z
y1
y1
y2
y2
Q
J1
Q
C
K1
Q
Q
J2
C
K2
Clock
Figure 8.24
Application Equation Method for Deriving
Excitation Equations -- Example 8.8
x
x
y1 y2
0
1
00
0
0
01
0
1
y1 y2
0
1
00
0
1
01
0
1
y2
11
1
0
11
1
0
10
1
0
y1
10
1
1
Y2
Y1
Figure 8.25
Sequence Recognizer for 01 Sequence -Example 8.9
1/0
1/0
A
(a)
1/0
A
0/0
A
0/0
B
(b)
B
0/0
1/0
A
(c)
Figure 8.26
0/0
1/1
(d)
B
0/0
Synthesis of the 01 Recognizer with SR Flip-flops
x
x
0
yk
1
0
1
0
1
A B/0 A/0
0
1
0
0
0
0
B B/0 A/1
1
1
0
1
0
1
(a) State table
yk + 1
z
(b) Transition table and output map
x
0
1
S
C
0
0
d
R
1
0
1
x
yk
x
yk
x
0
1
0
1
0
1
d
0
yk
S
(c) Excitation maps
Q
Q
yk
Clock
R
z
(d) Logic diagram
Clock
x
S=x
R=x
y
z
0 1
1
0
0
1
0
1
0
1
01
1
0
0
1
1
0
01
1
0
0
1
(e) Timing diagram
Figure 8.27
0
1
0
1
Realization of 01 Recognizer with T Flip-flops
yk
0
0
x
1
1
x
T
0
C
1
0
1
T
(a) Clocked T flip-flop
excitation map
yk
0
x
Clock
(b) Clocked T flip-flop
implementation
1
yk
0
x
1
0
1
0
0
d
d
1
d
d
1
0
1
J
K
(c) Clocked JK excitation maps
Figure 8.28
Q
Q
y
Design of a Recognizer for the Sequence 1111 -Example 8.11
0/0
A
0/0
B
1/0
x
1/1
0/0
C
1/0
1/0
0
1
A
A/0
B/0
B
D
A/0 C/0
A/0 D/1
C
A/0 D/0
D
0/0
(a) State diagram
(b) State table
x
y1ky2k
x
y1ky2k
0
1
00
00
01
01
00
11
10
0
1
00
0
0
10
01
0
0
00
11
11
0
1
00
11
10
0
0
y1k+1y2k+1
z
(c) Transition table
(d) Output map
Figure 8.29
SR Realization of the 1111 Recognizer
x
y 1 ky 2 k
0
1
00
0
0
01
0
11
10
y 1 ky 2 k
x
0
1
00
d
d
1
01
d
0
0
d
11
1
0
0
d
10
1
0
S1
y 1 ky 2 k
R1
x
0
1
00
0
1
01
0
11
10
x
y 1 ky 2 k
0
1
00
d
1
0
01
1
1
0
d
11
1
0
0
1
10
d
0
S2
Figure 8.30
R2
Clocked T and JK Realizations of the 1111
Recognizer
x
y1ky2k
0
x
y1ky2k
1
0
1
0
1
00
0
0
00
01
0
1
01
1
1
11
1
0
11
1
0
10
1
0
10
0
1
T(a)
T
1 Clocked T excitation maps 2
x
y1ky2k
0
1
00
0
0
01
0
11
10
x
y1ky2k
0
1
00
d
d
1
01
d
d
d
11
d
d
10
x
y 1ky 2k
0
1
00
0
1
d
01
d
1
0
11
1
0
10
J1
0
1
00
d
d
d
01
1
1
d
d
11
1
0
0
1
10
d
d
K
J
(b)1 Clocked JK excitation maps 2
x
y1 y2
K2
x
y1 y2
0
1
0
1
00
0
0
00
0
1
01
0
1
01
0
0
11
0
1
11
0
1
10
0
1
10
0
1
y2
y1
Y1
(c) Excitation K-maps
x
y 1k y 2k
Y2
Figure 8.31
Clocked JK Flip-Flop Realization of a 1111
Recognizer
Clock
J1
Q
y1
C
x
K1
Q
J2
Q
C
K2
z
Figure 8.32
Q
y2
Design of a 0010 Recognizer
0/0
0/0
A
B
1/0
C
0/0
0/1
D
E
A
Come here for an
incorrect input x = 0
G
B
0/0
1/0
0/1
C
D
0/0
1/0
G
Come here for an
incorrect input x = 1
F
1/0
1/0
E
1/0
F
(b)
(a)
0/0
0/0
0/0
0/0
0/0
A
B
1/0
G
1/0
B
0/1
C
0/0
1/0
A
0/0
D
E
1/0
1/0
1/0
1/0
0/1
C
D
0/0
0/0
0/0
G
1/0
1/0
F
E
1/0
1/0
F
1/0
(c)
(d)
x
0
1
A
B/0
F/0
B
C/0
F/0
C
G/0
D/0
x
A
0/0
0
1
B/0
A/0
D
E/1
F/0
B
C/0
A/0
E
C/0
F/0
C
G/0
D/0
F
B/0
F/0
D
B/1
A/0
G
G/0
F/0
G
G/0
A/0
(e)
1/0
G
1/0
1/0
A
0/0
(f)
B
0/0
0/1
1/0
(g)
Figure 8.33
0/0
1/0
C
D
Design of a Serial Binary Adder
Shift register A
Shift register B
ai
bi
Serial
adder
si
aibi/si
00/0
01/1
10/1
01/0
10/0
11/1
11/0
0
1
ci-1 = 0 00/1 ci-1 = 1
(b)
(a)
ai
bi
ai b i
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
ci-1
0
1
0
1
0
1
0
1
(c)
ci
0
0
0
1
0
1
1
1
Si
si
0
1
1
0
1
0
0
1
Ci
D
C
Clock
(d)
Figure 8.34
Q
Ci-1
Design of a Four-State Up/Down Counter
x
z=0
z=1
0
1
0
1
0 1
3
z=3
1 0
1
0
2
z=2
(a) State diagram
x
0
1
0
1/0
1
y 1ky 2k
0
1
3/0
00 01
11
2/1
0/1
01 10
00
2
3/2
1/2
11 00
10
3
0/3
2/3
10 11
01
y1 k + 1 y2 k + 1
(c) Transition table
(b) State table
x
y1 y2
x
0
y1 y2
1
0
1
00
0
d
1
d
00
1
d
1
d
01
1
d
0
d
01
d
1
d
1
11
d
1
d
0
11
d
1
d
1
10
d
0
d
1
10
1
d
1
d
J1
K1
J1
K1
J2
K2
J2
K2
(d) Excitation maps
Figure 8.35
An Implementation of the Up/Down Counter
Clock
x
1
J1
C
K1
Q
J1
C
K1
Q
y1
Q
y2
Q
Figure 8.36
LEDs
Design a BCD Counter
y3 k y2 k y1 k y0 k
x
0
1
0000 0000 0001
0001 0001 0010
x
0
1
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
9
9
9
0
0010 0010 0011
0011 0011 0100
0100 0100 0101
0101 0101 0110
0110 0110 0111
0111 0111 1000
1000 1000 1001
1001 1001 0000
1010 dddd dddd
1011 dddd dddd
1100 dddd dddd
1101 dddd dddd
(a)
1110 dddd dddd
1111 dddd dddd
y3 k + 1 y2 k + 1 y1 k + 1 y0 k + 1
(b)
Figure 8.37 (a) and (b)
Design of the BCD Counter (con’t)
y3 k y2 k y 1 k y0 k
x
x
x
x
x
x
x
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0000
0
0
d
d
0
0
d
d
0
0
d
d
0
1
d
d
0001
0
0
d
d
0
0
d
d
0
1
d
d
d
d
0
1
0010
0
0
d
d
0
0
d
d
d
d
0
0
0
1
d
d
0011
0
0
d
d
0
1
d
d
d
d
0
1
d
d
0
1
0100
0
0
d
d
d
d
0
0
0
0
d
d
0
1
d
d
0101
0
0
d
d
d
d
0
0
0
1
d
d
d
d
0
1
0110
0
0
d
d
d
d
0
0
d
d
0
0
0
1
d
d
0111
0
1
d
d
d
d
0
1
d
d
0
1
d
d
0
1
1000
d
d
0
0
0
0
d
d
0
0
d
d
0
1
d
d
1001
d
d
0
1
0
0
d
d
0
0
d
d
d
d
0
1
1010
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
1011
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
1100
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
1101
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
1110
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
1111
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
J3
K3
J2
K2
J1
(c)
Figure 8.37 (c)
K1
J0
K0
Realization of the BCD Counter Design
y1 k y0 k
y 2 k y3 k
00
01
11
10
00
01
11
10
00
0
d
d
0
0
d
d
0
01
0
d
d
0
0
d
d
0
11
0
d
d
d
1
d
d
d
10
0
d
d
d
0
d
d
d
x=0
x=1
(d)
x
y3
J3
C
K3
y2
y1
J2
J1
C
C
K1
K2
y0
J0
C
K0
Clock
Lights
(e)
Figure 8.37 (d) and (e)
K-map For Y1 in Example 8.16
y
y3
y3
0
0
d
0
0
0
d
0
0
0
d
0
1
1
d
0
y0
1
1
d
y0
d
y1
0
0
d
d
1
1
d
d
y1
1
1
d
d
y2
y2
Figure 8.38
Robot Controller Floor Plan -- Example 8.17
Exit
Bottom view
of robot
Sensor
(X)
Movable
blocks
Robot
Wheels
Figure 8.39
Robot Controller Design
0/00
A
0/00
D
0/00
C
1/10
0
x
y1 y2
1
1
00
0
0
01
0
11
10
y1 y2
B C/00 B/01
C C/00 D/10
01 11/00 01/01
11 11/00 10/10
D A/00 D/10
10 00/00 10/10
Y1Y2/z1z2
(c)
x
0
1
00
0
1
0
01
0
0
1
11
0
1
10
z1
y1 y2
x
0
1
00
0
0
1
01
1
0
0
11
0
0
10
z2
1
00 00/00 01/01
x
0
0
A A/00 B/01
NS/z1z2
(b)
0/00
x
y1 y2
y1 y2
B
X/Z1/Z2
1/10
(a)
x
1/01
1/01
y1 y2
0
1
00
0
1
0
01
1
1
1
1
11
1
0
0
1
10
0
0
Y1
(d)
Y2
(e)
Figure 8.40 (a) -- (e)
Robot Controller Realization
x
z1
z2
Q1
J1
Q1
K1
Q2
J2
Q2
K2
Clock
(f)
Figure 8.40 (f)
Candy Machine Controller Design -- Example 8.18
R
N
Coin
detector D
Release
candy
Control
unit
Release
change
C
(a)
ND/RC
00/00
0
10/10,
01/11
00/00 15
10/00
01/00
00/00
5
01/00
10/00
01/10
10
10/00
00/00
(b)
Figure 8.41
Algorithmic State Machines (ASMs)
State_Name
Moore outputs
(a)
0
Input
(b)
Figure 8.42
1
Mealy
outputs
(c)
ASM Representation of a Mealy Machine
z=0
A
1/0
0
1
X
0/0
A
B
0/1
X/Y
z=0
1/1
0/0
1/0
C
B
1
X
(b)
z=1
0
z=0
z=0
C
0
X
z=1
1
(a)
Figure 8.43
ASM Representation of a Moore Machine
A
z=0
0
1
X
0
B
z=1
0
X
A/0
1
1
1
1
B/1
0
0
C/0
(b)
C
z=0
0
X
Figure 8.44
1
(a)
Eight-Bit Two’s Complementer ASM -Example 8.19
A
Look for
first 1 bit
z=0
0
x
1
z=1
B
Complement
remaining bits
z=1
0
x
z=0
1
Figure 8.45
Binary Multiplier Controller -- Example 8.20
Start
Register A
Register Q
4
A
0
M
Multiplier
Q
Multiplicand
CNT
0
Muliplier
0
4
Cout
4
4
Add
Q0
Sum
Adder
2-bit
counter
1
A
A+M
4
0
4
Product
C0
Control
unit
4
Register M
Q0
Shift
Halt
Shift right A: Q
CNT
CNT + 1
Muliplicand
Halt
StartAdd Shift
Register control signals
(a)
0
C0
1
(b)
Figure 8.46
Halt
1
One-Hot State Assignments
State
A
B
C
D
Sequential Assignment
y1y0
00
01
10
11
Table 8.1
One-hot Assignment
y3y2 y1y0
0001
0010
0100
1000
ASM Design Using One-Hot State Assignments
Clock
DA
C
QA
Begin
State A
A
State A
Clock
DA C
DB C
State B
QA
QB
B
DB
...
...
State B
...
A
C
DC C
State C
QB
QC
B
C
(a)
(b)
Figure 8.47 (a) -- (b)
ASM Design Using One-Hot Assignments (con’t)
Clock
DA
State A
C
QA
0
State B
Inputs
Moore
Aoutput
x
1
z=1
Mealy
z output
DA
State C
C
QB
(c)
Figure 8.47 (c)
DA
C
QC
One-hot Design of A Multiplier Controller -Example 8.21
Clock
Begin
DA
C
Begin
QA
Clock
Start
DA
Q0
C
QA
x
DB
C
QB
z
Add
DC
C
DB
QC
Shift
C0
C
QB
Start
DD
C
(b)
QD
Halt
(a)
Figure 8.48
Incompletely Specified Circuits -- Detonator
(Example 8.22)
x
Detonator
z
A
1/0
0 /0
B
1/0
C
(b)
(a)
x
0
1
A
A/0 B/0
B
C
-/-/-
C/0
D/0
D
-/-
-/1
(c)
Figure 8.49
1/0
D
1/1
-
Detonator Example K-maps
y 2y
x
y 2y 1
0
1
00
00
01
01
dd
11
10
y 2y
x
0
1
00
0
0
10
01
d
dd
dd
11
dd
11
10
y2k+1y1k+1
1
y2y
x
0
1
00
0
0
0
01
d
d
1
11
d
0
10
1
z
0
1
00
0
1
1
01
d
1
d
d
11
d
d
d
0
10
d
1
T2
Figure 8.50
x
1
T1
Detonator Realization
y1
x
T1
C
Q
Q
y2
T2
C
Clock
Figure 8.51
Q
Q
z
Sate Assignments and Circuit Realization
x
y 2y 1
y 2y 1
x
0
1
0
1
00
1
0
00
1
d
0
0
01
0
0
01
1
0
0
0
11
0
1
11
d
d
1
0
10
d
1
10
d
d
0
1
D2
D1
D2
D1
x
0
y2 y 1
1
00
0d/1 00/0
01
10/0 00/0
11
dd/0 10/1
10
dd/d 01/1
Y2Y1/z
z
(a)
y2y1
x
0
(b)
y2y1
1
(c)
x
0
y2y1
1
x
0
1
00
0
d
0
0
00
0
d
0
d
00
d
d
0
d
01
1
1
0
1
01
1
d
0
d
01
d
1
d
1
11
d
d
0
1
11
d
d
d
0
11
d
d
d
1
10
d
d
1
1
10
d
d
d
1
10
d
d
1
1
T2
T1
T2
T1
J2
K2
J2
K2
J1
K1
J1
K1
(d)
(e)
Figure 8.52