Transcript Chapter 3

Digital Fundamentals
CHAPTER 3
Logic Gates
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 1
Logic Gates
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•
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Inverter
AND Gate
OR Gate
Exclusive-OR Gate
NAND Gate
NOR Gate
Exclusive-NOR Gate
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 2
The Inverter
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 3
The Inverter
Truth table
Boolean expression
0 = LOW
1 = HIGH
Pulsed waveforms
The output of an inverter is always the
complement (opposite) of the input.
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 4
The AND Gate
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 5
The AND Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
The output of an AND gate is HIGH only
when all inputs are HIGH.
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 6
The AND Gate
3-Input AND Gate
4-Input AND Gate
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 7
The OR Gate
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 8
The OR Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
The output of an OR gate is HIGH
whenever one or more inputs are HIGH
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 9
The OR Gate
3-Input OR Gate
4-Input OR Gate
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 10
The NAND Gate
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 11
The NAND Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
The output of a NAND gate is HIGH
whenever one or more inputs are LOW.
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 12
The NAND Gate
3-Input NAND Gate
4-Input NAND Gate
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 13
The NOR Gate
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 14
The NOR Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
The output of a NOR gate is LOW
whenever one or more inputs are HIGH.
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 15
The NOR Gate
3-Input NOR Gate
4-Input NOR Gate
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 16
Exclusive-OR and Exclusive-NOR Gates
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 17
Exclusive-OR Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
The output of an XOR gate is HIGH
whenever the two inputs are different.
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 18
Exclusive-NOR Gate
Boolean expression
Truth table
0 = LOW
1 = HIGH
Pulsed waveforms
The output of an XNOR gate is HIGH
whenever the two inputs are identical.
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 19
Programmable Logic
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 20
Programmable Logic
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•
•
•
Programmable AND array
Programmable link technology
Device programming
In-system programming (ISP)
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 21
Programmable Logic
• Programmable AND array
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 22
Programmable Logic
Programmable link technology
• Fuse technology
• Anti-fuse technology
• EPROM technology
• EEPROM technology
• SRAM technology
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 23
Programmable Logic
Device programming
• Design entry
– Text entry
– Graphic (schematic) entry
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 24
Programmable Logic
• In-system programming (ISP)
– Joint Test Action Group (JTAG)
– Imbedded processor
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 25
Fixed-Function Logic
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 26
Fixed-Function Logic
• CMOS
• TTL
Floyd
Digital Fundamentals, 9/e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Slide 27