Transcript Document

Logic Design with MSI Circuits
• วัตถุประสงค์ของบทเรี ยน
 รู้จกั วงจรประเภท MSI
 เข้าใจการทางานของวงจร MSI ที่มีใช้อยูท่ วั่ ไป
 สามารถประยุกต์ใช้วงจร MSI ในการออกแบบ
วงจรลอจิกแบบต่างๆ ได้
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Type of Circuits
Type of ci rcuits
Number o f gates
Small-scale integration (SSI)
1-10
Medium-scale integ ration (MSI)
10-100
Large-scale integration (LSI)
100-1,000
Very-large-scale integration (VLSI)
1,000 up
หมายเหตุ หนังสื อบางเล่มแบ่งวงจรที่มีเกตตั้งแต่ 1,000,000 เกต
ขึ้นไป ให้อยูใ่ นกลุุ่ม ULSI (Ultra-large-scale integration)
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Multiplexers (MUXs)
- also called a data selector
Input lines consist of
- data lines: 2n lines
- select lines: n lines
- there may or may not be an
enable line
Output line:
- output line: 1 line
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Multiplexer Function
-Truth table of a 4:1 multiplexer (without enable)
Select inputs
Output
S1
S0
Y
0
0
I0
0
1
I1
1
0
I2
1
1
I3
Y  S1.S0 .I0  S1.S0 .I1  S1.S0 .I2  S1.S0 .I3
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Multiplexer Function
-Truth table of a 4:1 multiplexer (with enable)
Enable
Select inputs
Output
E
S1
S0
Y
0
X
X
0
1
0
0
I0
1
0
1
I1
1
1
0
I2
1
1
1
I3
Y  E.(S1.S0 .I0  S1.S0 .I1  S1.S0 .I2  S1.S0 .I3 )
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Logic Circuit Design using Multiplexer
Advantages
 No need for logic simplification
 Minimize the IC package count
 Simplify the logic design
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Logic Design using MUX
Case 1: Number of inputs is equal to
number of select lines
Design procedure
 Identify the decimal number corresponding to
each minterm in the expression
 Connect logic 1 level to input lines
corresponding to these numbers
 Connect logic 0 level to the others
 Connect inputs to selected lines
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Case1: Inputs = Select lines
a three-variable function using a 8-to-1-line multiplexer
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Example
f(x,y,z) = m(0,2,3,5) using 8-to-1-line multiplexer
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Logic Design using MUX
Case 2: Number of inputs is higher
than number of select lines
Procedure 2.1: Reduce the number
of inputs to the number of select
lines by
• inspection
• k-map
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Case 2
-Truth table of a 3 variable logic circuit
Input
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Output
Input
Output
x
y
z
Y
x
y
z
Y
0
0
0
f0
0
0
1
f1
0
1
0
f2
0
1
1
f3
1
0
0
f4
1
0
1
f5
1
1
0
f6
1
1
1
f7
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Case2.1: Reducing Inputs
a 3-variable Boolean function using a 4-to-1-line multiplexer
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Example
f(x,y,z) = m(0,2,3,5) using a 4-to-1-line multiplexer
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Reducing Inputs with K-map
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Example
f(x,y,z) = m(0,2,3,5)
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More on Reducing Inputs
(a) Applying input variables y and z to the S1 and S0 select lines.
(b) Applying input variables x and y to the S0 and S1 select lines.
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Example
f(x,y,z) = m(0,2,3,5)
(a) Applying input
variables y and z to the
S1 and S0 select lines.
(b) Applying input
variables x and y to the
S0 and S1 select lines.
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Reducing 4-input to 3-input
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Example
f(w,x,y,z) = m(0,1,5,6,7,9,12,15)
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Logic Design using MUX
Procedure 2.2: Use multiplexer tree
when number of inputs exceeds the largest
number of inputs on available ICs
Can be done by one of these two techniques
- connect the MSB input to the enable/strobe
input
- connect the MSB input to another
multiplexer
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Demultiplexers/Decoders
-Performs the reverse operation of a multiplexer
Input lines are:
- 1 data line
- n select lines
- maybe 1 enable
Output lines are
- 2n output lines
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Application Example
A multiplexer/demultiplexer arrangement for
information transmission
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Decoders
A n-to-2n-line decoder is a circuit that only one of
the output line responds to the n-input data.
Number of input:output is n:2n
(Note: a demultiplexer is a decoder
with
an enable input acting as a data
input line
A BCD to 7-segment decoder is a circuit that 7-bit
output will make each segment of the 7-segment lit
according to the 4-bit input
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3-to-8-line Decoder
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Application Example
การใช้ 3-to-8-line decoder และ
or-gate ในการสร้างวงจร
f1(x2,x1,x0) = m(1,2,4,5) และ
f2(x2,x1,x0) = m(1,5,7)
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Application Example
f1(x2,x1,x0) =
m(0,1,3,4,5,6)
= m(2,7) and
f2(x2,x1,x0) =
m(1,2,3,4,6)
= m(0,5,7)
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Application Example
f1(x2,x1,x0) = M(0,1,3,5) and f2(x2,x1,x0) = M(1,3,6,7)
(a) Using output or-gates.
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(b) Using output nor-gates.
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3-to-8-line decoder using nand-gates
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Application Example
f1(x2,x1,x0) = m(0,2,6,7) and f2(x2,x1,x0) = m(3,5,6,7)
(a) Using output and-gates. (b) Using output nand-gates.
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Decoder with Enable Input
And-gate 2-to-4-line decoder with an enable input
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Encoders
- Similar to decoders
- Usually number of input lines are more than
number of output lines
Number of input:output is 2n:n
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Binary Adders
Binary Half-Adder
xi
0
0
1
1
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yi
0
1
0
1
si
0
1
1
0
Binary Full-Adder
xi
0
0
0
0
1
1
1
1
ci
0
0
0
1
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yi
0
0
1
1
0
0
1
1
ci-1
0
1
0
1
0
1
0
1
si
0
1
1
0
1
0
0
1
ci
0
0
0
1
0
1
1
1
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Binary Full-Adder
si = xi'.yi'.ci+xi'.yi.ci'+xi.yi'.ci'+xi.yi.ci
ci+1 = xi.yi + xi.ci + yi.ci
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Parallel Binary Adder
Parallel (ripple) binary adder
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Binary Subtractor
Binary Half-Subtractor
Binary Full-Subtractor
xi
0
0
1
1
xi
0
0
0
0
1
1
1
1
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yi
0
1
0
1
di
0
1
1
0
bi+1
0
1
0
0
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yi
0
0
1
1
0
0
1
1
bi
0
1
0
1
0
1
0
1
di
0
1
1
0
1
0
0
1
bi+1
0
1
1
1
0
0
0
1
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Parallel Binary Subtractor
Parallel (ripple) binary subtractor
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Parallel Binary Adder/Subtractor
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Carry Look-ahead Adder
From Boolean expression of the F.A.
ci+1 = xiyi + (xi+yi)ci
Let’s
gi = xiyi
(carry-generate function)
and pi = (xi+yi) (carry-propagate function)
c1
= g0 + p0c0
c2
= g1 + p1c1
= g1 + p1(g0 + p0c0)
= g1 + p1g0 + p1p0c0
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Carry Look-ahead Adder (cont.)
c3
= g2 + p2c2
= g2 + p2(g1 + p1g0 + p1p0c0)
= g2 + p2g1 + p2p1g0 + p2p1p0c0
...
ci+1 = gi + pigi-1 + pipi-1gi-2 + ...
+ pipi-1...p1g0 + pipi-1...p0c0
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Carry Look-ahead Adder (cont.)

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BCD Arithmetic
BCD Adder
 Using a 4-bit binary adder to perform two one digit
BCD addition
 a decimal 6 (binary 0 1 1 0) will be added to the
result if the sum output is an invalid BCD or if a
carry at the MSB is 1
 each BCD adder can be cascaded for adding several
BCD digits
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BCD Arithmetic
BCD Subtractor
 Convert the subtrahend to its 9’s complement form
 Add the result to the minuend
 If the summation result is an invalid BCD code or
if the carry from the MSB is 1, add decimal 6
(binary 0 1 1 0) and the end around carry (EAC) to
this sum
 If the summation result is a valid BCD code, the
result is negative and in the 9’s complement form
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Nine’s Complementer Circuit
A 9’s complementer circuit is
 a circuit designed to convert a decimal digit (in
BCD code) to its 9’s complement
 created by adding binary 1 0 1 0 to the 1’s
complement of the number (ignore the carry)
(Proof is left as a student exercise)
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Arithmetic Logic Unit (ALU)
• performs arithmetic and logic operations
(depends on the selected mode)
• Read details and example in section 6.6
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Comparators
A comparator is a circuit that compares the magnitudes of two
binary numbers
Input: Ai, Bi, Gi, Ei, Li
Gi= 1 when Ai-1Ai-2...A1A0 > Bi-1Bi-2...B1B0
Ei= 1 when Ai-1Ai-2...A1A0 = Bi-1Bi-2...B1B0
Li= 1 when Ai-1Ai-2...A1A0 < Bi-1Bi-2...B1B0
Output: Gi+1, Ei+1, Li+1
Gi+1= 1 when AiAi-1...A1A0 > BiBi-1...B1B0
Ei+1= 1 when AiAi-1...A1A0 = BiBi-1...B1B0
Li+1= 1 when AiAi-1...A1A0 < BiBi-1...B1B0
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1-bit Comparator
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Other MSI Circuits
• Parity generators/checkers
• Code converters
 BCD-to-binary converter
 Binary-to-BCD converter
• Priority encoders
 Decimal-to-BCD encoder
 Octal-to-binary Encoder
• Decoder/drivers for display devices
 BCD-to-decimal decoder/driver
 BCD-to-7-segment decoder/driver
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