Transcript Document

DFT Compiler 1
2004.12
Synopsys Customer Education Services
© 2005 Synopsys, Inc. All Rights Reserved
Synopsys 30-I-011-SSG-007
Course Materials

Student Workbook

Lab Book

Reference Materials

Course Evaluations
i- 2
Facilities
Building Hours
Emergency
Phones
EXIT
Messages
Restrooms
Smoking
Meals
Recycling
Please turn off cell phones and pagers
i- 3
Workshop Prerequisites
You should have experience in the following areas:

Digital IC design

Verilog or VHDL

UNIX and X-Windows

A Unix based text editor
i- 4
Curriculum Flow
Physical Compiler 1
The
Power
of
Tcl
The
Power
of
Tcl
The
Power
of
3 workshops Tcl
3 workshops
workshops
atat333skill
levels
at 3skill
skilllevels
levels
Design Compiler 1
PrimeTime:
PrimeTime 1
Advanced STA
Constraint Debugging
PrimeTime:
Signal Integrity
DFT Compiler 1
ATPG with TetraMAX
Astro 1
Astro XTalk
i- 5
Target Audience
SoC Design and Test engineers who need
to identify and fix DFT violations in their
RTL or gate-level designs, insert scan into
multi-million gate SoCs, and export design
files to ATPG and P&R tools.
i- 6
Introductions

Name

Company

Job Responsibilities

EDA Experience

Main Goal(s) and Expectations for this Course
i- 7
Galaxy™ Design Platform
Synopsys Manufacturing Test Solution
Design Services
Test Synthesis
DFT Compiler™, SoCBIST
DFT
Compiler
Power
Compiler
DesignWare
JupiterXT
Physical Compiler
Astro
•
•
Milkyway
PrimeTime SI
Module
Compiler
Design Compiler
Unified DFT synthesis, verification and
test signoff
Significant test cost reduction
ATPG
TetraMAX® ATPG, DSMTest, TenX
Star-RCXT
Hercules
• Leading-edge ATPG with comprehensive
support for delay related defects
Proteus
i- 8
External DFT and ATPG Flows
RTL
Which flow(s) do you use now
or plan to use in the future?
Unplaced Netlist
with Scan
DC/DFTC
No Scan | Test Ready | Scan Existing
G2PG Flows
RTL2PG Flow
PC/DFTC
Floorplan
Floorplan
Tool
Mapped and Placed Design
With Scan Chains
Astro
P&R Design with Scan
(restitched if from DC/DFTC)
TetraMAX
i- 9
1-Pass Test Suite: Environment Overview
RTL Source
Design Compiler/Physical Compiler Environment
BSD Compiler
DFT Compiler
IEEE-1149.1
1-Pass Test Synthesis
Boundary
Scan Netlist
BSDL
Test Vectors
Scan Design
(Gates)
Setup Info
STIL File
TetraMAX Environment
TetraMAX ATPG
Sequential Fault Simulator
Bridging Faults
IDDQ
Transition Delay
Path Delay
i- 10
DFT Compiler TM

RTL Rule Checking: In-depth testability analysis
at RT Level:


Removes unpredictability from back-end design process

DFT synthesis

Shadow LogicDFT synthesis
Scan Synthesis: Transparent scan implementation:


Helps designers write “test-friendly” RTL
AutoFix: Automatic correction of scan DRC violations:


1-Pass Scan Synthesis
Seamlessly optimize all design constraints — timing, area, power
and test (logical and physical domain)
Hierarchical Scan Synthesis: Leverage existing flows
and test models to gain multi-million gate capacity and
improved performance (logical and physical domain)
i- 11
Top-Down Scan Insertion Flow
Unmapped
DFT Flow
Read RTL Design
Violations?
Constraints
Met?
Mapped
DFT Flow
Start
Create Test Protocol
Read Design and
Test Protocol
DFT Check
DFT Check
Specify Scan Paths
Test-Ready Compile
Preview
Timing, Area
Violations?
Insert Scan Paths
Coverage
Violations?
Handoff Design
End
i- 12
DFT Compiler Test-Ready or Unmapped Flow
Test-Ready Flow

Start point is RTL
(unmapped) design
RTL
Source

IDEAL starting point

1-Pass Scan synthesis
achieved by taking RTL
directly to a scan
synthesized design
DFT Compiler
DFT synthesis, test drc, test
coverage preview
Scan-inserted
Design
Testability
Reports
i- 13
DFT Compiler Mapped Flow
Mapped Flow

Start point is gate-level
(mapped) design with
no scan circuitry yet

DFT Compiler performs
scan cell replacement
and scan chain
synthesis
Gate-Level
Source
DFT Compiler
DFT synthesis, test drc, test
coverage preview
Scan-inserted
Design
Testability
Reports
i- 14
DFT Compiler Existing Scan Flow
Existing Scan Flow

Start point is gate-level
design that already
includes scan cells and
chains

DFT Compiler performs
scan chain extraction &
test DRCs in
preparation for
TetraMAX ATPG
Gate-Level
Source
DFT Compiler
DFT synthesis, test drc, test
coverage preview
Scan-inserted
Design
Testability
Reports
i- 15
Bottom-Up Scan Insertion Flow
Block
DFT Flow
Violations?
Violations?
RTL DFT Flow
RTL DFT Flow
Read Block and
Test Protocol
Read Block and
Test Protocol
···
Block
DFT Flow
DFT Check
DFT Check
Specify Scan Paths
Specify Scan Paths
Preview
Preview
Insert Scan Paths
Insert Scan Paths
Coverage
Coverage
Handoff Block
···
Top-Level DFT
Violations?
Violations?
Handoff Block
i- 16
Methods for High Capacity Scan Synthesis

DFT Compiler
UDRC
RSS
ILMs
DC-XG
PC-XG
Uses TetraMAX DRC for consistency and faster runtime
Avoids “test uniquification” and just stitches the scan chains
Test Models, Interface Logic Models (ILMs) with Test Models:


DFT Compiler
UDRC
RSS
Test Models
ILMs
Rapid Scan Synthesis (RSS):


PC
Unified Design Rule Checking (UDRC):


DC
Highly reduced scan models of gate-level designs
XG Mode
 New DC/PC infrastructure increases capacity and reduces runtime
i- 17
Workshop Goal
Use DFT Compiler to check RTL and mapped
designs for DFT violations, insert scan chains
into very large multi-million gate designs in
either logical or physical flows, and export all
the required files for downstream tools.
i- 18
Agenda
DAY
1
1
Understanding Scan Testing
2
DFTC User Interfaces
3
Creating Test Protocols
4
DFT for Clocks and Resets
i- 19
Workshop Objectives: Day 1

Define the test protocol for a design

Perform DFT checks at both the RTL and
gate-levels

State common clocking and reset/set design
constructs that cause typical DFT violations

Automatically fix certain DFT violations at the
gate-level using AutoFix
i- 20
Agenda
DAY
2
5
DFT for Tristate Nets
6
DFT for Bidirectional Pins
7
DFT for Embedded Memories
8
Top-Down Scan Insertion
i- 21
Workshop Objectives: Day 2


State design constructs that cause typical DFT
violations and how you can workaround these
problems:

Tristate nets

Bidirectional pins

Embedded memories
Insert scan to achieve well-balanced top-level scan
chains and other scan design requirements
i- 22
Agenda
DAY
3
9
Exporting Design Files
10
High Capacity DFT Flows
11
Test Data Volume Reduction
12
Conclusion
CS Customer Support
i- 23
Workshop Objectives: Day 3

Write a script to perform all the steps in the DFT flow,
including exporting all the required files for ATPG and
Place & Route

Customize the test initialization sequence, if needed

Modify a bottom-up scan insertion script for full
gate-level designs to use Test Models/ILMs with RSS
and run it

Preview top-level chain balance using test
models/ILMs after block level scan insertion and
revise block level scan architecture as needed to
improve top-level scan chain balance

Insert additional observe test points to reduce
number of ATPG patterns
i- 24
Icons Used in this Workshop
Lab Exercise
Caution
Recommendation
Definition of
Acronyms
For Further Reference
Question
“Under the Hood”
Information
Group Exercise
i- 25
Test Automation Docs are on SolvNet!
i- 26