Transcript + x
Threshold Logic for Nanotechnologies
Zvi Kohavi and Niraj K. Jha 1
Introductory Concepts
Threshold element or gate :
x 1 w 1 x 2 w 2 w n T y x n
Example:
y = f
(
x
1
,x
2
,x
3 )
=
(1,2,3,6,7) =
x
1
’x
3
+ x
2
x 1 x 2
2 -1 1 1 2
y x 3
2
MOBILEs
Monostable-bistable transition logic element (MOBILE): a resonant tunneling diode (RTD) and heterostructure field-effect transistor (HFET) nanotechnology based threshold element • Rising edge-triggered, current-controlled gate • Serially-connected load and driver RTDs • RTD-HFET structures in parallel to the load (driver) RTDs perform positive (negative) weighting of inputs • Area of RTDs: corresponds to weight • Difference in the areas of the driver and load RTDs: threshold
Clk
RTD Load
w
1
w
2 Positive weight inputs
x
1
x
2
f
HFET
-w
3
T x
3 Driver Negative weight input 3
Majority Gates
Majority gate: a special type of threshold element • A three-input majority gate: produces a 1 if a majority of its inputs are 1
M
(
x
1
,x
2
,x
3 )
= x
1
x
2
+ x
2
x
3
+ x
1
x
3 • Can be implemented as a threshold element: with
w
1
T
= 2 =
w
2 =
w
3 = 1 and • Acts like an AND (OR) gate when one of its inputs is tied to 0 (1) Nanotechnology implementations: single-electron box (SEB) quantum cellular automata (QCA), Input
x 1
Input
x 2
1 0 Device cell Output cell 1 Inputs
x 1 x 2 x 3
Node 1 C C C
V d
C L C j C 0 C L C j Node 2 C C
f 3
Output terminal C
f 2 f 1
Input x
3
Input capacitor Output capacitor 1 QCA SEB 4
Minority Gates
Minority gate: produces a 1 if a majority of its inputs are 0
m
(
x
1
,x
2
,x
3 )
= x
1
’x
2
’ + x
2
’x
3
’ + x
1
’x
3
’
• Acts like a NAND (NOR) gate when one of its inputs is tied to 0 (1) Nanotechnology implementation: tunneling phase logic (TPL) Clock 1 C i Clock 2 J 1 J 2 J 3 Pump TPL C j J 4 Pump 5
Capabilities and Limitations of Threshold Logic
Threshold gate: generalization of conventional gates • More powerful than conventional gates because it can realize a larger class of functions • Any conventional gate can be realized with a threshold gate • Thus, threshold gates are functionally complete Example: NAND implementation
x 1
-1 -1
x 2
-1 1 2
y
6
Is Every Switching Function Realizable by One Threshold Element?
Answer: No Example: Let
f
(
x
1
,x
2
,x
3
,x
4 )
= x
1
x
2
+ x
3
x
4 • Output value must be 1: for
x
1
x
2
x
3
’x
4
’, x
1
’x
2
’x
3
x
4 • Output value must be 0: for
x
1
’x
2
x
3
’x
4
, x
1
x
2
’x
3
x
4
’
• Since the requirements in the inequalities are conflicting, no threshold value can satisfy them – Thus, the function is not realizable by a single threshold element 7
Basic Problem of Threshold Logic
Given a switching function
f
(
x
1 ,
x
2 , …,
x n
): determine whether it is realizable by a single threshold element, and if it is, find appropriate weights and threshold • Such a function is called a threshold function Straightforward approach: Solve a set of 2
n
linear, simultaneous inequalities Example: Let
f
(
x
1 ,
x
2 ,
x
3 ) = (0,1,3) Combination 0:
T
must be negative Combinations 2, 4:
w
2 ,
w
1 must be negative Combinations 3, 5:
w
2 must be greater than
w
1 Combination 1:
w
3 is greater than Thus, or equal to
T w
3
T > w
2
> w
1
w
1
= -
2
, w
2
= -
1
, w
3
=
1
, T = -
1/2 8
Sensitivity to Variations
Limitation: Due to variations in input and supply voltages, the weighted sum may deviate from its prescribed value and cause circuit malfunction • Restrictions imposed on the number of inputs and threshold
T
• Introduce defect tolerances: non-negative and 9
Elementary Properties
Weight-threshold vector:
V
= {
w
1 ,
w
2 , …,
w n
;
T
} Let
f
(
x
1 ,
x
2 , …,
x n
) be realized by inputs
x
1 ,
x
2 , …,
x j
’, …,
x n V
1 = {
w
1 ,
w
2 , …,
w j
, …,
w n
;
T
}. If
x j
complemented, it can be realized by
V
2 is = {
w
1 ,
w
2 , …,-
w j
, …,
w n
;
T-w j
} with From
V
1 : When
V
2 replaces
V
1 and
x j
’ replaces
x j
: where
g
is realized by
V
2
g
and
x j f
are identical: = 0 and
x j
= 1 since the equations reduce to each other for both 10
Important Conclusions
If a function is realizable using a single threshold element, then by an appropriate choice of complemented and uncomplemented input variables: a realization with any sign distribution is possible Corollary: if a function is realizable by a single threshold element, then it is realizable by an element with only positive weights 11
Important Property
If
f
(
x
1 ,
x
2 , …,
x n
) is realizable by a single threshold element with
V
1 = {
w
1 ,
w
2 , …,
w n
;
T
}, then its complement is realizable by a single threshold element with
V
2 = {-
w
1 ,-
w
2 , …,-
w n
;-
T
} From
V
1 : Multiplying both sides by -1: Thus,
f’
is realizable by
V
2 12
Synthesis of Threshold Networks
Unate functions: function
f
(
x
1 ,
x
2 , …,
x n
) is positive (negative) in variable
x i
there exists a disjunctive or conjunctive expression for the function in which
x i
only appears in uncomplemented (complemented) form if If
f
is either positive or negative in
x j
: it is said to be unate in
x i
Example:
f = x
1
x
2
’ + x
2
x
3
’
in
x 2
is positive in
x
1 and negative in
x 3
, but not unate If
f
(
x
1 ,
x
2 , …,
x n
) is unate in each of its variables: then it is called unate Example:
f = x
1
’x
2
+ x
1
x
2
x
3
’
is unate since it can be simplified to
x
1
’x
2
+ x
2
x
3
’
Example:
f = x
1
x
2
’ + x
1
’x
2 is not unate in either variable 13
Unate Functions
If
f
(
x
1 ,
x
2 , …,
x n
) is positive in
x i
: then it can be expressed as and vice versa If
f
(
x
1 ,
x
2 , …,
x n
) is negative in
x i
: then it can be expressed as and vice versa 14
Geometric Representation
n
-cube: contains 2
n
vertices, each of which represents an assignment of values to
n
variables and thus corresponds to a minterm • a line is drawn between every pair of vertices which differ in just one variable • Vertices for which the function is 1 (0) called: true (false) vertices Example: Three-cube representation for
f = x’y’ + xz
(1,1,1) (1,1,0) (0,1,1) (1,0,1) (0,1,0) (1,0,0) (0,0,1) (0,0,0) 15
Partial Ordering
Partial-ordering relation between vertices of the
n
-cube: (
a
1 ,
a
2 , …,
a n
) (
b
1 ,
b
2 , …,
b n
) if and only if for all
i
,
a i
b i
• Partially ordered set of vertices: a lattice • (0,0, …,0): least vertex • (1,1, …,1): greatest vertex • Some pair of variables incomparable: e.g., (0,0, …,0,1) and (1,0, …,0,0) Without loss of generality: concentrate on positive unate functions Example: relabel
x
1
’x
2
x
3
’ + x
2
x
3
’x
4 • By reconverting the latter:
as x
1
x
2
x
3
+ x
2
x
3
x
4 possible to determine the original function 16
Unate Function Theorem
Theorem 1:
f
(
x
1 ,
x
2 , …,
x n
) is unate if and only if it is not a tautology above partial ordering exists, such that for every pair of vertices, (
a
1 ,
a
2 , …,
a n
) and (
b
1 ,
b
2 , …,
b n
), if (
a
1 ,
a
2 , …,
a n
) is a true vertex and and the (
b
1 ,
b
2 , …,
b n
) (
a
1 ,
a
2 , …,
a n
), then (
b
1 ,
b
2 , …,
b n
) is also a true vertex of
f
Minimal true vertex: vertex
S j
A true vertex
S i < S i
is said to be minimal if no other true Maximal false vertex: A false vertex
S i
false vertex
S j > S i
is said to be maximal if no other Example: For
x
1
x
2
+ x
3
x
4 • Minimal true vertices:
S
1 = (1,1,0,0),
S
2 • Thus, every vertex greater than
S
1 (1,1,1,0), (0,1,1,1) or
S
2 = (0,0,1,1) must be a true vertex: e.g., – These vertices correspond to
x
1
x
2
x
3
f
and
x
2
x
3
x
4 , which are covered by 17
Linear Separability
For an
n
-cube representation for threshold functions: linear equation
w
1
x
1
+ w
2
x
2
+ … + w n x n = T
corresponds to an (
n
-1)-dimensional hyperplane that cuts through the
n
-cube • Since
f
= 0 when
w
1
x
1 • and
f
= 1 when
+ w
2
x
2
+ … + w n x n < T w
1
x
1
+ w
2
x
2
+ … + w n x n
T
the hyperplane separates the true vertices from the false ones Such a function is called a linearly separable function • Thus, every threshold function is linearly separable, and vice versa 18
Theorems
Theorem 2: Every threshold function is unate Theorem 3: Given an expression for a unate switching function,
f
(
x
1 ,
x
2 , …,
x n
), replace
x j
by
x k ’
, resulting in
f
(
x
1 ,
x
2 , …,
x n
). If
g
is not a threshold function, then neither is
f
Example: Let
f = x
1
x
2
+ x
3
x
4 • To determine if
f
is a threshold function: replace
x
2 by
x
3
’
• This results in
g = x
1
x
3
’ + x
3
x
4 • Since
g
is not unate in
x
3 , it is not a threshold function • Hence, neither is
f
19
Identification and Realization of Threshold Functions
Procedure: 1. Test the given function
f
for unateness 2. If it is unate, convert it into another function
g
that is positive in all its variables 3. Find all minimal true and maximal false vertices of
g
4. Derive and solve a system of
pq
inequalities, corresponding to the
p
true and
q
maximal false vertices minimal For minimal true vertex
A B
= {
b
1
,b
2
, …,b
n }, write
w
1
a
1
+ w
2
a
2
+ … + w
n
a
n = {
> w
1
a b
1 1
,a
2
, …,a + w
2
b
2 n } and maximal false vertex
+ … + w
n
b
n 20
Identification Example
Example: Given
f = x
1
x
2
x
3
’x
4
+ x
2
x
3
’x
4
’
1. Reduce to
f = x
1
x
2
x
3
’ + x
2
x
3
’x
4
’,
which is unate
2. g = x
1
x
2
x
3
+ x
2
x
3
x
4 3. Minimal true vertices: (1,1,1,0), (0,1,1,1); Maximal false vertices: (1,1,0,1), (1,0,1,1), (0,1,1,0) 4.
p
= 2 and
q
= 3 yields 6 inequalities: 5. Necessary constraints that must be satisfied:
V
= {1,2,2,1; 9/2} for
g
=>
V
= {1,2,-2,-1; 3/2} for
f
21
Map-based Synthesis of Two-level Threshold Networks
Decomposition of non-threshold functions: into two or more factors that are threshold functions Admissible pattern: a pattern of 1 cells that can be realized by a single threshold element • An admissible pattern may be in any position on the map • An admissible pattern for functions of three variables is also an admissible pattern for functions of four or more variables • Since the complement of a threshold function is also a threshold function, patterns of 0 cells are also admissible • Select a minimal number of admissible patterns such that each 1 cell is covered by at least one admissible pattern 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 22
Synthesis Example
Example: For
f
(
x
1
,x
2
,x
3
,x
4 ) = (2,3,6,7,10,12,14,15), find a minimal threshold-logic realization
x 3 x 4 x 1 x 2
00 01 11 10 00 1 01 11 1 1 1 10 1 1 1 1
g h
(
a
) Map for
f
exhibiting two admissible patterns
x 1 x 1 x 2 x 3 x 4 x 2 x 1 x 3 x 4
1 -2 3 1 5 2
g x 2 x 3
1 2 1 -1 5 2
x 4
(
b
) Threshold elements realizing the admissible patterns
x 1 x 2
-2 1 3 1 5 2
g x 3
1 3 2 1 -1 5 2
x 4
(
c
) Threshold-logic realization of
f f h
23
Another Synthesis Example
Example: For
f
(
x
1
,x
2
,x
3
,x
4 ) = (3,5,7,10,12,14,15), find a minimal threshold-logic realization
x 3 x 4 x 1 x 2
00 01 11 10 00 1 01 1 1 11 1 1 1 10 1 (
a
) Map showing a minimal set of prime implicants which cover
f
.
x 1 x 3 x 4 x 1 x 2 x 4 x 2 x 3 x 4 x 1 x 2 x 4 x 1 x 3 x 4
(
b
) AND-OR realization of
f f x 3 x 4 x 1 x 2
00 00 01 11 10 1 01 1 1 11 1 1 1 10 1
x 2 x 1 x 3 x 4 x 1
1 -1 1 2 2 1 2
g x 2
1 3 1 2 1 2 -1
x 3 x 4
(
d
) A threshold-logic realization of
f
2 1 2
f
(
c
) Map showing the admissible pattern realized by each threshold element.
24
Synthesis of Multi-level Threshold Networks
Example: One-to-one map from the following network to a threshold network requires seven threshold elements (including the inverter) and five logic levels – quite sub-optimal • Reason: some nodes can be collapsed into a single threshold node
x 1 x 2 x 3 n 4 n 5 n 3 x 5 n 1 f x 1 x 4 x 6 x 7 n 2
(
a
) Switching network Assuming a fanin restriction of four: • Collapse
f = n
1
+ n
2 to
n
3
x
5
+ x
6
x
7 • Since
f
is not threshold: split it into
n
1
+ x
6
x
7 , where
n
1 • Since • Since
n n
1 1
+ x = n
synthesize
n
6 4 4
x x
7 5 is threshold:
+ n
5
x
5 synthesize
n
1 is threshold:
x 1 = x
1
x
2
x
3 and
x 2 x 3 n
5
= x
1
’x
4 , which are both threshold
x 1
next 1 1 1 3
n 4 x 5 n 5
-1 1 1
x 4 = n
3
x
5 1 2 1 3
n 1 x 6 x 7
2 1 1 2 (
b
) Equivalent threshold network 25
f
General Synthesis Procedure
Procedure: 1. Start with a multi-output algebraically-factored switching network
G
2. Process each primary output of
G
• If the node represents a binate function, split into multiple nodes and process recursively • • If the node is unate and is also a threshold function, save it in the threshold network and process its input nodes recursively Else, split the unate node into two or more nodes that are threshold functions 3. Terminate procedure when all the nodes in
G
are mapped to threshold nodes 26
Mapping Threshold Networks to MOBILEs
MOBILE: a self-latching threshold gate because its output is valid only when the clock is high Four-phase clocking: same clock phase all signals to any threshold element must arrive in the • Ensured by inserting buffers as necessary 27
MOBILE Example
Full-adder: 1 Level:
a b c i
1 1 1 2
2 3
c 0
1 -2 1 1 1
s
Level:
a b c i
threshold 1 (
a
) Network before inserting buffers 2 3
1 1 1 2
c 0
1 -2 1 1 1
s
threshold buffer (
b
) Network after inserting buffers
w a
=1
T
= 1 2 CLK
f a
1 1 2
f
28
Synthesis of Multi-level Majority/Minority Networks
Realizable pattern: pattern of 1 cells realizable by a majority gate • For three-input positive functions: 10 realizable patterns • Removing the restriction that function be positive:
x 3 x 1 x 2
00 01 11 10
x 3 x 1 x 2
00 01 11 10
x 3 x 1 x 2
00 01 11 38 realizable patterns 10 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1
x 1 = M(x 1 , 1, 0) = M(x 1 , 0, 1) x 2 = M(1, x 2 , 0) = M(0, x 2 ,1) x 3 = M(1, 0, x 3 ) = M(0, 1, x 3 ) x 3 x 1 x 2
00 0 01 1 11 1 10 1 1 1 1 1
x 2 + x 3 = M(1, x 2 , x 3 ) x 1 x 2 x 3
00 0 1 01 1 1 11 1 1 10 1 1
x 1 + x 2 = M(x 1 , x 2 , 1) x 3 x 1 x 2
00 0 01 1 1 1 11 1 1 10 1 1
x 1 + x 3 = M(x 1 , 1, x 3 ) x 3 x 1 x 2
00 0 01 1 11 1 10 1
x 1 x 2 = M(x 1 , x 2 , 0) x 3 x 1 x 2
00 0 01 1 1 11 1
x 2 x 3 = M(0, x 2 , x 3 )
10
x 3 x 1 x 2
00 0 01 1 11 10 1
x 1 x 3 = M(x 1 , 0, x 3 )
1
x 1 x 2 x 3
00 0 01 11 1 10 1 1 1 1
x 1 x 2 + x 1 x 3 +x 2 x 3 = M(x 1 , x 2 , x 3 )
29
Synthesis Example
x 1 x 2 x 3 x 1 x 2 x 3 x 1 x 2 x 3 x 1 x 2 x 3
Example: Consider
f = x
1
’x
2
’x
3
’ + x
1
’x
2
x
3 • Naïve approach:
+ x
1
x
2
x
3
’ + x
1
x
2
’x
3 decompose network into two-input AND and OR gates and replace each such gate by a reduced majority gate • However, if we make full use of the three inputs of a majority gate: only four gates necessary • Minority network: can be obtained from a majority network using De Morgan’s theorem
f x 1 x 2 x 3 x 1 x 2 x 3 x 1 x 2 x 3 M f 1 M f 2 M f 3 M f x 1 x 2 x 3 x 1 x 2 x 3 x 1 x 2 x 3 m f 1 m f 2 m f 3
(
c
) (
a
) (
b
)
m f
30
General Synthesis Procedure
Procedure: 1. Start with a multi-output algebraically-factored switching network
G
2. Decompose G into a network in which nodes have at most three inputs • If the node represents a majority function, move on to the next node • If a common literal exists in all the product terms of the node function, factor it out and perform AND/OR mapping on it • • If a common literal does not exist, check to see if the node can be implemented with fewer than four AND/OR nodes Else, map the node onto at most four majority gates using a Karnaugh-map based procedure Example: • Consider
f = x
1
x
2
’+ x
2
’x
3 With AND/OR mapping, three majority gates are needed: • –
f
1
= x
1
x
2
’, f
2
= x
2
’x
3
, f = f
1 However, since literal
x
2
’ + f
2 can be factored out: – This requires only two majority gates
f = f
1
x
2
’
where
f
1
= x
1
+x
3 31
K-map based Procedure
Given the map of a node function
n
with at most three inputs: 1. Find a realizable pattern
f
1 2. Find a second realizable pattern
f
2 based on
f
1 and
n
3. Find the third realizable pattern
f
3 – based on Realizable patterns chosen such that
f
1 ,
n = M f
( 2
f
1 and
,f
2
,f
3
n
)
= f
1
f
2
+f
2
f
3
+f
1
f
3
4. f
1 – – may contain makeup minterms that are not minterms of
n
A minterm (maxterm) of
n
must also be a minterm (maxterm) of at least two of the three functions,
f
1 ,
f
2 and
f
3 0 » For finding
f 2
: if a minterm (maxterm) of
n
(maxterm) of
f
1 0 is not a minterm » For finding
f
3 : if a minterm (maxterm) of
n
(maxterm) of both
f
1 and
f
2 is not a minterm 0 5. On failure to find
f
3 , backtrack to find new
f
2 32
Synthesis Example
x 3 x 1 x 2
0 Example: 00 1 01 11 1 Consider
f = x
1
’x
2
’x
3
’ + x
1
’x
2
x
3 Step 1: find
f 1
10
x 3 x 1 x 2
00 01 11 10
x 1 x 2 x 3
0 1
1
1 0
+ x
1
x
2
x
3
’ + x
1
x
2
’x
3 Compute 1 00 01 11 10 1 1 1 1 1 1 1
n = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3
(
a
)
f 1 = x 1 x 2 + x 2 x 3 + x 1 x 3 = M(x 1 , x 2 , x 3 )
(
b
)
x 1 x 2 x 3
0 00 Compute 0 01 11 0 10 1
x 3 x 1 x 2
00 Step 2: find
f 2
01 11 10 0 1 1 1
1
1 (
c
)
x 1 x 2 x 3
0 00 1 Update 1 01 11 1 10 1
x 1 x 2 x 3 x 1 x 2 x 3 x 1 x 2 x 3
(
d
)
x 1 x 2 x 3
00 0 1 Update 0 01 11 0
f 2 = x 1 x 2 + x 2 x 3 + x 1 x 3 = M(x 1 , x 2 , x 3 )
(
e
) 10
x 1 x 2 x 3
00 Step 3: find
f 3
01 11 10 0 1 1 1 0 1 1 (
g
)
f 3 = x 1 x 2 + x 2 x 3 + x 1 x 3 = M(x 1 , x 2 , x 3 )
(
h
) (
f
)
M f 1 M f 2 M f 3 M f
33